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I'm trying to synchronize the ADC's (both A and B) to the PWM,
as described in Mot. app. note AN1933/D, section 5.2. I am using center-aligned PWM technique (Fig. 5-4 in app note). I want to have a sample at a specific location in each PWM half-cycle. I have two questions related to this. The first is: since I'm running both ADCA and ADCB, do I have to have operate both PWM-A and PWM-B also, since to the limit of my understanding ADCA is connected to PWMA, via timer TC2; and ADCB is connected to PWMB via TC3? The second question is more general: operation of ADC end-of-conversion ISR's. I want configure things to read ADC values in the ADC end-of-convert ISR's. The problem I seem to be having is that I enter the ISR and do the processing, then exit it - then I immediately reenter the same ISR - even if I halt the CPU in the IDE, and disable the ADC, and restart processor. It appears that, once I get the end-of-cycle ISR once, I will continue to keep reentering it - even if the ADC is disabled. So - I assume I obviously have to take some action to clear the pending ISR - but I can't figure out what it is. The following are the ADCA and ADCB register setting I'm using: ADCR1 0x1805 ADCR2 0x0003 ADCCC 0x0000 ADLST1 0x3210 ADLST2 0x7654 ADSDIS 0 ADSTAT 0 ADLSTAT 0 ADZCSTAT 0 Timer 2 register settings, same for TC2 and TC3 (desire 10us delay with 40 MHz IPbus): TC2_CTRL 0xD035 TC2_SCR 0x0101 TC2_CMP1 0 TC2_CMP2 0 TC2_CAP 0 TC2_LOAD 0x018D TC2_HOLD 0 TC2_CNTR 0 Finally, PWM A and B. Desire 40 us period, with 40MHz IPbus. PWMCTL 0x0811 Thanks very much in advance for any help or insight - or example code. Even if someone just tells me how to clear pending ISR - that would be a helpful. - Bill Schintler |
DSP56F807: Synchronization of on chip ADC to PWM
Started by ●July 18, 2003
