Forums

Measuring PWM with DSP56F80x

Started by Bende Georg August 26, 2003
Hello all,

I'm trying to measure the duty percentage of a PWM signal in the range of
200Hz-2KHz.
I configured 2 timer channels in the following way:

/*.
Quad Timer A0 configuration
----------------------------
Count mode: Edge of 2nd source triggers primary count till compare
Primary count source: Prescaler (IP BUS clock divide by 128)
Secondary count source: Counter #0 input pin
Input polarity: True polarity
Output polarity: True polarity
Input capture mode: Load the capture register on falling edge of input
Output capture mode: Asserted while counter is active
Count once: Count until compare and stop
Count direction: Count up
Coinit disabled, Master mode disabled, Output disabled
Interrupts: None

/*.
Quad Timer A1 configuration
----------------------------
Count mode: Edge of 2nd source triggers primary count till compare
Primary count source: Prescaler (IP BUS clock divide by 128)
Secondary count source: Counter #0 input pin
Input polarity: Inverted polarity
Output polarity: True polarity
Input capture mode: Load the capture register on falling edge of input
Output capture mode: Asserted while counter is active
Count once: Count until compare and stop
Count direction: Count up
Coinit disabled, Master mode disabled, Output disabled
Interrupts: None

This way A0 should count the time from the rising to the falling edge, and A1
counts from falling to rising - it seemed very easy.
Now I have 2 problems:
The capture register contains very often false values or zero although IEF bit
is set; I can't measure the signal reliably. (It's not a matter of the signal
quality, it is very nice shaped)
Other problem is that I'd like to let this measurement run in the background.
But the timer module doesn't work as described in the User's Manual:
14.6.7 Triggered-Count Mode ...Odd edges restart the counting. ...
Actually, counting isn't restarted, only continued if anoter edge occurs. After
a capture occurs I have to set the IEF bit manually, and this way it's very
uncomfortable.
Does anyone have an idea how to do this better?

Best wishes,
Georg Bende
Softwareentwickler
Abteilung Elektronik
Dr. Fritz Faulhaber GmbH & Co KG
Daimlerstr. 23
71101 Schaich
Tel: +49 7031 638294




Hi Georg,

A couple thoughts on the subject. The User Manual on the QuadTimers
is the worst of all the chapters on giving useful information.

You say below that you "set the IEF bit", just make sure you are
Clearing this bit to re-enable a capture. I use the interrupt to
read the capture reg and clear the IEF flag but you could just do
that after reading and then clearing the capture reg in the
background.

To initialize the counter after the capture you could set up another
timer, say A2, as a Master with a very short count and set your
counters Co-Channel Init bit, Co Init, to do this for you. However,
I am not sure if the Init will clear the Capture register or not (the
manual does not give any good info on this and I could not get it out
of Tech Support either).

Pete --- In , "Bende Georg" <georg.bende@f...>
wrote:
> Hello all,
>
> I'm trying to measure the duty percentage of a PWM signal in the
range of 200Hz-2KHz.
> I configured 2 timer channels in the following way:
>
> /*.
> Quad Timer A0 configuration
> ----------------------------
> Count mode: Edge of 2nd source triggers primary count till
compare
> Primary count source: Prescaler (IP BUS clock divide by 128)
> Secondary count source: Counter #0 input pin
> Input polarity: True polarity
> Output polarity: True polarity
> Input capture mode: Load the capture register on falling edge
of input
> Output capture mode: Asserted while counter is active
> Count once: Count until compare and stop
> Count direction: Count up
> Coinit disabled, Master mode disabled, Output disabled
> Interrupts: None
>
> /*.
> Quad Timer A1 configuration
> ----------------------------
> Count mode: Edge of 2nd source triggers primary count till
compare
> Primary count source: Prescaler (IP BUS clock divide by 128)
> Secondary count source: Counter #0 input pin
> Input polarity: Inverted polarity
> Output polarity: True polarity
> Input capture mode: Load the capture register on falling edge
of input
> Output capture mode: Asserted while counter is active
> Count once: Count until compare and stop
> Count direction: Count up
> Coinit disabled, Master mode disabled, Output disabled
> Interrupts: None
>
> This way A0 should count the time from the rising to the falling
edge, and A1 counts from falling to rising - it seemed very easy.
> Now I have 2 problems:
> The capture register contains very often false values or zero
although IEF bit is set; I can't measure the signal reliably. (It's
not a matter of the signal quality, it is very nice shaped)
> Other problem is that I'd like to let this measurement run in the
background. But the timer module doesn't work as described in the
User's Manual:
> 14.6.7 Triggered-Count Mode ...Odd edges restart the counting. ...
> Actually, counting isn't restarted, only continued if anoter edge
occurs. After a capture occurs I have to set the IEF bit manually,
and this way it's very uncomfortable.
> Does anyone have an idea how to do this better?
>
> Best wishes,
> Georg Bende
> Softwareentwickler
> Abteilung Elektronik
> Dr. Fritz Faulhaber GmbH & Co KG
> Daimlerstr. 23
> 71101 Schaich
> Tel: +49 7031 638294




You should set the Count Once = 0 which keeps counter
non-stop running. So that you can capture the edge of
the pulse. If you try to capture the pulse width, you
should use Gated-Count Mode.

C.W.
--- Bende Georg <> wrote:
> Hello all,
>
> I'm trying to measure the duty percentage of a PWM
> signal in the range of 200Hz-2KHz.
> I configured 2 timer channels in the following way:
>
> /*.
> Quad Timer A0 configuration
> ----------------------------
> Count mode: Edge of 2nd source triggers primary
> count till compare
> Primary count source: Prescaler (IP BUS clock
> divide by 128)
> Secondary count source: Counter #0 input pin
> Input polarity: True polarity
> Output polarity: True polarity
> Input capture mode: Load the capture register on
> falling edge of input
> Output capture mode: Asserted while counter is
> active
> Count once: Count until compare and stop
> Count direction: Count up
> Coinit disabled, Master mode disabled, Output
> disabled
> Interrupts: None
>
> /*.
> Quad Timer A1 configuration
> ----------------------------
> Count mode: Edge of 2nd source triggers primary
> count till compare
> Primary count source: Prescaler (IP BUS clock
> divide by 128)
> Secondary count source: Counter #0 input pin
> Input polarity: Inverted polarity
> Output polarity: True polarity
> Input capture mode: Load the capture register on
> falling edge of input
> Output capture mode: Asserted while counter is
> active
> Count once: Count until compare and stop
> Count direction: Count up
> Coinit disabled, Master mode disabled, Output
> disabled
> Interrupts: None
>
> This way A0 should count the time from the rising to
> the falling edge, and A1 counts from falling to
> rising - it seemed very easy.
> Now I have 2 problems:
> The capture register contains very often false
> values or zero although IEF bit is set; I can't
> measure the signal reliably. (It's not a matter of
> the signal quality, it is very nice shaped)
> Other problem is that I'd like to let this
> measurement run in the background. But the timer
> module doesn't work as described in the User's
> Manual:
> 14.6.7 Triggered-Count Mode ...Odd edges restart the
> counting. ...
> Actually, counting isn't restarted, only continued
> if anoter edge occurs. After a capture occurs I have
> to set the IEF bit manually, and this way it's very
> uncomfortable.
> Does anyone have an idea how to do this better?
>
> Best wishes,
> Georg Bende
> Softwareentwickler
> Abteilung Elektronik
> Dr. Fritz Faulhaber GmbH & Co KG
> Daimlerstr. 23
> 71101 Schaich
> Tel: +49 7031 638294
>


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