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AW: Re: Measuring PWM with DSP56F80x

Started by Bende Georg August 27, 2003
Thanks for your comments, at least I'm now sure that it's not my English that
isn't enough to understand the Manual. :)
What I've discovered, that I can't use the same input pin once inverted and once
with true polarity. The manual states that
"14.7.2.7 Input Polarity Select (IPS)-Bit 9
When set, this bit inverts the polarity of a signal being driven on to a package
pin from an
external source. It does not invert the polarity of an input signal when the
signal is being
driven by another timer group."
Actually, "timer group" is meant to be "timer" and in this case it is
self-explanatory why my efforts failed. Another good question why it worked
totally unpredictable....

> You say below that you "set the IEF bit", just make sure you are
> Clearing this bit to re-enable a capture. I use the interrupt to
> read the capture reg and clear the IEF flag but you could just do
> that after reading and then clearing the capture reg in the
> background.

Well, I don't want to use an additional interrupt, there are a lot of interrupts
already making hard the job of my processor, now one wich comes with a very high
frequency (the user may put a higher frequency although not recommended in the
manual) can be a real danger for the product reliability.
Of course I'm clearing IEF to 0.
I have to make it very complicated with an internal state machine- NEC
processors have two capture regs for this purpose, it seems Motorola isn't
suited for this by hardware means.

> You should set the Count Once = 0 which keeps counter
> non-stop running. So that you can capture the edge of
> the pulse. If you try to capture the pulse width, you
> should use Gated-Count Mode.

The problem is that in this case I will get very inaccurate results; without the
use of capture register, the two timers will drift away and there will be only a
narrow frequency window where I can use it reliably.

Best regards,
Georg Bende
Softwareentwickler
Abteilung Elektronik
Dr. Fritz Faulhaber GmbH & Co KG
Daimlerstr. 23
71101 Schaich
Tel: +49 7031 638294 > -----Ursprgliche Nachricht-----
> Von: Pete Becher [mailto:]
> Gesendet: Mittwoch, 27. August 2003 15:44
> An:
> Betreff: [motoroladsp] Re: Measuring PWM with DSP56F80x > Hi Georg,
>
> A couple thoughts on the subject. The User Manual on the QuadTimers
> is the worst of all the chapters on giving useful information.
>
> You say below that you "set the IEF bit", just make sure you are
> Clearing this bit to re-enable a capture. I use the interrupt to
> read the capture reg and clear the IEF flag but you could just do
> that after reading and then clearing the capture reg in the
> background.
>
> To initialize the counter after the capture you could set up another
> timer, say A2, as a Master with a very short count and set your
> counters Co-Channel Init bit, Co Init, to do this for you. However,
> I am not sure if the Init will clear the Capture register or not (the
> manual does not give any good info on this and I could not get it out
> of Tech Support either).
>
> Pete > --- In , "Bende Georg" <georg.bende@f...>
> wrote:
> > Hello all,
> >
> > I'm trying to measure the duty percentage of a PWM signal in the
> range of 200Hz-2KHz.
> > I configured 2 timer channels in the following way:
> >
> > /*.
> > Quad Timer A0 configuration
> > ----------------------------
> > Count mode: Edge of 2nd source triggers primary count till
> compare
> > Primary count source: Prescaler (IP BUS clock divide by 128)
> > Secondary count source: Counter #0 input pin
> > Input polarity: True polarity
> > Output polarity: True polarity
> > Input capture mode: Load the capture register on falling edge
> of input
> > Output capture mode: Asserted while counter is active
> > Count once: Count until compare and stop
> > Count direction: Count up
> > Coinit disabled, Master mode disabled, Output disabled
> > Interrupts: None
> >
> > /*.
> > Quad Timer A1 configuration
> > ----------------------------
> > Count mode: Edge of 2nd source triggers primary count till
> compare
> > Primary count source: Prescaler (IP BUS clock divide by 128)
> > Secondary count source: Counter #0 input pin
> > Input polarity: Inverted polarity
> > Output polarity: True polarity
> > Input capture mode: Load the capture register on falling edge
> of input
> > Output capture mode: Asserted while counter is active
> > Count once: Count until compare and stop
> > Count direction: Count up
> > Coinit disabled, Master mode disabled, Output disabled
> > Interrupts: None
> >
> > This way A0 should count the time from the rising to the falling
> edge, and A1 counts from falling to rising - it seemed very easy.
> > Now I have 2 problems:
> > The capture register contains very often false values or zero
> although IEF bit is set; I can't measure the signal reliably. (It's
> not a matter of the signal quality, it is very nice shaped)
> > Other problem is that I'd like to let this measurement run in the
> background. But the timer module doesn't work as described in the
> User's Manual:
> > 14.6.7 Triggered-Count Mode ...Odd edges restart the counting. ...
> > Actually, counting isn't restarted, only continued if anoter edge
> occurs. After a capture occurs I have to set the IEF bit manually,
> and this way it's very uncomfortable.
> > Does anyone have an idea how to do this better?
> >
> > Best wishes,
> > Georg Bende
> > Softwareentwickler
> > Abteilung Elektronik
> > Dr. Fritz Faulhaber GmbH & Co KG
> > Daimlerstr. 23
> > 71101 Schaich
> > Tel: +49 7031 638294 > ------------------------ Yahoo! Groups Sponsor
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