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Hi, I'm looking for ideas on implementing memory mapped input-output with the DSP56F807 that also has external static RAM. Running at 80Mhz puts some tough timing requirements on the design. Here's what we have working: The controller design uses the DSP56F807. There is a CPLD on the board connected to the address and data bus from the DSP, along with the memory control signals it is used to generate some additional memory mapped input/output "ports" in the CPLD. The RAM chip is the GSI GS72116ATP-8. The memory interface is the same as on the EVM board except the chip-enable input to the RAM is generated by decoding the DSP's address and control signals. To get the timing to work I have to enable wait states on-the-fly when accessing the memory that is mapped to the external I/O in the CPLD. This is not really a problem except that in order to prevent getting interrupted while in the slowed-down state I have to disable interrupts. If interrupts are not disabled it may go off into a critical interrupt service routine with wait states on and run too slow. For the most part this is OK except that it adds some jitter to when the ISR that samples my analog feedback signal runs because it may have to wait until the "wait-stated" code that is accessing the I/O runs. Anybody know of a no wait-state memory-mapped I/O design that works at 80Mhz? Or maybe some other creative ways to solve this problem?? Thanks for taking a look, Kirk |
Memory mapped input-output on DSP56F807
Started by ●September 17, 2003
