The Mot 56002 has a PLL control register (PCTL) that allows for
adjustments to clock via a multiplier factor (MF), and dividing
factor (DF). MF can range from 1 .. 4096, DF is 2^n, where n can
range from 0 .. 15 I believe. The external crystal is 4Mhz.
For some reason, let's say I wanted to implement a multiplication
factor of 1887, with a division factor of 2^8. That should give
me 4Mhz * 1887/256 = 29,484,375Mhz. My attempt to load the
PCTL with $0685fe (which is the above specifics) results in a loss
of lock condition with no subsequent re-acquire of lock.
To ensure that the clock source is indeed the output of the
divider instead of the VCO, I loaded a multiplier of 20 with a
division factor of 2. This resulted in a clock freq of 20Mhz,
and not 80Mhz (which is out of spec for my 66Mhz chip).
Anyone know what I am doing wrong?
Thanks in advance,