DSP56F807 questions

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Here are the answers:

Q. On the DSP56F801/803/805/807, the Quad Timer modules A and B share pins
      with Quadrature Decoder modules number zero and number one. If the shared
     pins are not configured as timer _outputs_, then the pins are available for
     as inputs to the Quadrature Decoder modules."

A. Yes

Q.  . "14.8.1 Timer Group A (DSP56F803, DSP56F805, and DSP56F807 only) Timer group
    A shares pins with Quadrature Decoder module zero. The decoder has primary
   ownership of the pins for inputs. The Decoder Control Register for
   Quadrature Decoder Zero (DEC0_DECCR) controls a switch matrix that connects
   Timer A inputs to the I/O pins, provides filtered input data, or a remapped
   data format. " so,  is the shared pins  possible to be configured as timer _inputs_,
    not outputs?

A. The shared pin can either use as output or input .If as output it has a fixed relationship . if as input it can be programmed such any these shared pin can be input to any of the timer(0-3)

Q   The Timer group A outputs are directly connected to the I/O pins

A. Yes

Q. In Table D-4 (D-14,D-15)  there are not pins, that connected to the group A
outputs.

A. 801 has no quadrature decoder

Q. Or group A outputs are directly connected to the I/O pins Quadrature
Decoder module zero? pins 147,148,149,150?

A. Yes

Q. And "If a timer's output is enabled, (when Scr OEN is set? ) its output
   will drive the I/O pin.", and I can't use the Quadrature Decoder module
   zero in this case

A. No, you can't use the Quadrature Decoder module
   zero in this case

Q. If a timer's output is disabled, (Scr OEN is reset ),  I can't use this
    output for cascading counts,  because output is in the tri-state?

A. yes, you still can use this output for cascading counts. It use different runs internal for cascading

Q. "The decoder module does not use the I/O pins for outputs. "
     Is it always, or when a timer's output is enabled?
    Whether I have access to signals "count" and "up/dn"  or to only PhaseA and
    PhaseB? 

A.  "count" value is  in registers. and "up/dn" are internal signals . It does not has any output pin for decoder.         Phi A , B, Index and Home are inputs to Decoder and output of an    

       encoder.

Q. Next "14.8.2 Timer Group B (DSP56F805 and DSP56F807 only)"

    There are print mistakes??

A. Yes, The first two should be PHASEA1, PHASEB1  

Q. Timer A, counter zero input/output pin is shared with Quadrature Decoder Zero
A. PHASEA0 pin shares for Output, PHASEA0 pin are shared with any of timer input (Timr 0-3)

Qs

Timer A, counter one I/O pin is shared with Quadrature Decoder One PHASEB0 pin.Zero??

PHASEB0 pin shares  for Output, PHASEB0 pin are shared with any of timer input (Timr 0-3)

Timer A, counter two I/O pin is shared with Quadrature Decoder Zero INDEX0 pin.
Timer A, counter three I/O pin is shared with Quadrature Decoder Zero HOME0 pin.

A. Same principles applys here. all timer output has fixed relationship with these 4 shared pins and all these shared pins can be programmed as input to either timer provided that you do not use Decoder

Appendix D, fig D-7 pin 136 is TDI, not TCI
yes, it should be TD1

-----Original Message-----
From: Andrew Shelkovenko [mailto:m...@omnisp.ru]
Sent: Thursday, April 25, 2002 7:56 PM
To: m...@yahoogroups.com
Subject: [motoroladsp] DSP56F807 questions

Hello!

Sorry for my  English.

I have some qustions about DSP56F807.

"10.1 Introduction
[...]
On the DSP56F801/803/805/807, the Quad Timer modules A and B share pins
with Quadrature Decoder modules number zero and number one. If the shared
pins are not configured as timer _outputs_, then the pins are available for
                                
use as inputs to the Quadrature Decoder modules."

But in 14.8.1 (14-21)

"14.8.1 Timer Group A (DSP56F803, DSP56F805, and DSP56F807 only) Timer group
A shares pins with Quadrature Decoder module zero. The decoder has primary
ownership of the pins for inputs. The Decoder Control Register for
Quadrature Decoder Zero (DEC0_DECCR) controls a switch matrix that connects
Timer A inputs to the I/O pins, provides filtered input data, or a remapped
data format. "

So,  is the shared pins  possible to be configured as timer _inputs_,
not outputs?

Next

"The Timer group A outputs are directly connected to the I/O
pins. "

In Table D-4 (D-14,D-15)  there are not pins, that connected to the group A
outputs.
Or group A outputs are directly connected to the I/O pins Quadrature
Decoder module zero? pins 147,148,149,150?

And "If a timer's output is enabled, (when Scr OEN is set? ) its output
will drive the I/O pin.", and I can't use the Quadrature Decoder module
zero in this case?
If a timer's output is disabled, (Scr OEN is reset ),  I can't use this
output for cascading counts,  because output is in the tri-state?

Next

"The decoder module does not use the I/O pins for outputs. "
Is it always, or when a timer's output is enabled?
Whether I have access to signals "count" and "up/dn"  or to only PhaseA and
PhaseB?

Next "14.8.2 Timer Group B (DSP56F805 and DSP56F807 only)"

There are print mistakes??

[...]
Timer A, counter zero input/output pin is shared with Quadrature Decoder Zero
PHASEA0 pin.

Timer A, counter one I/O pin is shared with Quadrature Decoder One PHASEB0 pin. 
                                                                                                      Zero??

Timer A, counter two I/O pin is shared with Quadrature Decoder Zero INDEX0 pin.
Timer A, counter three I/O pin is shared with Quadrature Decoder Zero HOME0 pin.
[...]
Timer group B shares pins with Decoder module one.
Timer B, counter zero I/O pin is shared with Quadrature Decoder One PHASE0 pin.
                                                                    ^^^^^^
                                                                    PHASEA1

Timer B, counter one I/O pin is shared with Quadrature Decoder One PHASE1 pin.
                                                                   ^^^^^^
                                                                  PHASEB1

Appendix D, fig D-7 pin 136 is TDI, not TCI
--------------------------
Next

14.8.3 Timer group C
14.8.3.2

"Note Timers two and  three can use the input pins allocated to timers
zero and one. Their outputs can be used by timers zero and one."

How I can to control the connection (commutation) pins of timers zero and
one to "Timers two and  three" ? Control register  can select primary and
secondary sour within the same timers group only.

14.8.4 Timer group D
Are the Timer group D (and C) outputs are directly connected to the I/O
pin, as Timer group a and B ?

14.6.3 Edge-Count Mode

If the Count Mode field is set to 010, the counter
will count the both edges of the selected clock source. This mode is useful
for counting the changes in the external environment such as a simple
encoder wheel.

Is the clock source connected to the primary or secondary input or both of
them?
--------------------

Thank you

With best regards, Andrew Shelkovenko.

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