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I still have the same problem with the Port A DSP56303

Started by Hernan Dario Herrera March 10, 2004
Hi again
 
Thanks to you who answer me the last time.
 
But I still have the same problem. When I send data to the port A I always get a wrong value. I already set up the AAR 0 to 3 and the BCG registers. But it never works fine.
 
This is the code I'm working with:
 
ADDRES EQU $C00010
ADDRESS EQU $C00020
XBASE EQU $000100
org x:XBASE
list1 dc $AAAAAA,$000000,$777777,$C52D6A,$A50F2F,$717D2F
       dc $E74FFF,$A88806,$DFFF14,$F00A00,$500E0F,$100F07
       dc $700D01,$800C04,$D00E09,$C00F67,$F00F03,$900A07
org p:START
movep   #$D00439,x:M_AAR1      ;not used
movep   #$C00431,x:M_AAR0      ; Address from C00000 to CFFFFF  
movep   #$AFBC31,x:M_AAR2     ;not used    
movep   #$B00C31,x:M_AAR3      ;not used
movep #$1F2421,x:M_BCR       
...
  move #list1,r0
 
  do #9,loop
  move x:(r0)+,b0
  nop
  move b0,x0
  move x0,x:ADDRES
loop
  nop
  do #9,loop1
  move x:(r0)+,a0
  nop
  move a0,x0
  move x0,x:ADDRESS
loop1
 jmp *
 
When I send the $AAAAAA data, I get $A5556A, and believe me, I'm not connecting the logic analizer wrong.
 
If anyone can help me, I'd appreciate it.
 
Thanks
 


Hernan Dario Herrera T.
Asistente de Investigaci
Pontificia Universidad Javeriana
Cali - Colombia






Moin,

Hernan Dario Herrera wrote:
> When I send the $AAAAAA data, I get $A5556A, and believe me, I'm not
> connecting the logic analizer wrong.

Really sure about this? The number of 1s/0s is correct, just a little bit
scrambled. And if you interface real SRAM instead of a logic analyzer,
you simply don't care about the scrambling as long as you read back what
you have written. Or as we say in germany: Wer viel misst misst Mist.

Ciao,
Stefan



If you're working on the DSP56303 EVM (you didn't say) are you aware
that the address and data bits are "scrambled" in the hardware
connection to external memory? For example, DSP data bits 0,1,2, and
3 are wired to memory chip bits 7,6,5, and 3, respectively. Similar
for other data bits and address bits. Check the schematic in the EVM
UM.
That said, the pattern that you are observing doesn't seem to be
resolved when you take the "scrambling" into account.

As an aside, anyone out there know why the bits are scrambled in
hardware? --- In , Stefan Stenzel <Stefan@S...>
wrote:
> Moin,
>
> Hernan Dario Herrera wrote:
> > When I send the $AAAAAA data, I get $A5556A, and believe me, I'm
not
> > connecting the logic analizer wrong.
>
> Really sure about this? The number of 1s/0s is correct, just a
little bit
> scrambled. And if you interface real SRAM instead of a logic
analyzer,
> you simply don't care about the scrambling as long as you read back
what
> you have written. Or as we say in germany: Wer viel misst misst
Mist.
>
> Ciao,
> Stefan



I would imagine it was done to make routing of the PCB easier.
 
Jacob
www.pontech.com


From: wygonski [mailto:j...@hei.org]
Sent: Thursday, March 11, 2004 10:41 AM
To: m...@yahoogroups.com
Subject: [motoroladsp] Re: I still have the same problem with the Port A DSP56303

If you're working on the DSP56303 EVM (you didn't say) are you aware
that the address and data bits are "scrambled" in the hardware
connection to external memory?  For example, DSP data bits 0,1,2, and
3 are wired to memory chip bits 7,6,5, and 3, respectively.  Similar
for other data bits and address bits.  Check the schematic in the EVM
UM. 
That said, the pattern that you are observing doesn't seem to be
resolved when you take the "scrambling" into account.

As an aside, anyone out there know why the bits are scrambled in
hardware?   --- In m...@yahoogroups.com, Stefan Stenzel <Stefan@S...>
wrote:
> Moin,
>
> Hernan Dario Herrera wrote:
> > When I send the $AAAAAA data, I get $A5556A, and believe me, I'm
not
> > connecting the logic analizer wrong.
>
> Really sure about this? The number of 1s/0s is correct, just a
little bit
> scrambled. And if you interface real SRAM instead of a logic
analyzer,
> you simply don't care about the scrambling as long as you read back
what
> you have written. Or as we say in germany: Wer viel misst misst
Mist.
>
> Ciao,
> Stefan


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It's a common practice to scramble the address and data lines to help
PCB layout. This is typically related to trace length. It really has no
affect on the usage of the memory...

--
dB

--- wygonski <> wrote:
> If you're working on the DSP56303 EVM (you didn't say) are you aware
> that the address and data bits are "scrambled" in the hardware
> connection to external memory? For example, DSP data bits 0,1,2, and
>
> 3 are wired to memory chip bits 7,6,5, and 3, respectively. Similar
> for other data bits and address bits. Check the schematic in the EVM
>
> UM.
> That said, the pattern that you are observing doesn't seem to be
> resolved when you take the "scrambling" into account.
>
> As an aside, anyone out there know why the bits are scrambled in
> hardware? > --- In , Stefan Stenzel <Stefan@S...>
> wrote:
> > Moin,
> >
> > Hernan Dario Herrera wrote:
> > > When I send the $AAAAAA data, I get $A5556A, and believe me, I'm
> not
> > > connecting the logic analizer wrong.
> >
> > Really sure about this? The number of 1s/0s is correct, just a
> little bit
> > scrambled. And if you interface real SRAM instead of a logic
> analyzer,
> > you simply don't care about the scrambling as long as you read back
>
> what
> > you have written. Or as we say in germany: Wer viel misst misst
> Mist.
> >
> > Ciao,
> > Stefan >


__________________________________