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The following is an FAQ about to appear on the Frescale website:
Ref # 24969 KBase DSP Level 1 Pending (1 of 2) Author Winters John (r54531) Abstract How can critical section code best be protected from interrupts? The effect of the pipeline must be included. Problem After masking interrupts in the SR register, the following instruction can be interrupted, the interrupt serviced, and control returned to the next instruction, exposing the critical section code to interruption. Solution Place one NOP after the instruction that masks the interrupts for the following parts: 5682x 5680x Place six NOP's after the instruction that masks the interrupts for the following parts: 5685x 568xxx Review older SDK code for compliance. Example for 80x: bfset #0x0300,SR ; mask interrupts nop ; allow for pipeline tfr y1,a ; this not to be seen in isr tfr y0,a ; isr should see this. bfclr #0x0300,SR ; allow interrupts again. HINT: NOP's may be replaced with instructions located prior to the start of the critical section.. this will save code space. Just be sure that the instructions take at least the equivalent number of cycles as the NOPS would have. Comments Categories for DSP 56800EVM Application Code General Interrupts Products for DSP 56800 DSP56852 DSP56853 DSP56854 DSP56855 DSP56857 DSP56858 DSP56F801 DSP56F802 DSP56F803 DSP56F805 DSP56F807 DSP56F826 DSP56F827 MC56F8322 MC56F8323 MC56F8345 MC56F8346 MC56F8347 MC56F8355 MC56F8356 MC56F8357 Created 2004-05-13 23:42:44 Modified 2004-05-17 19:18:01 Revision 2004-11-01 00:00:00 |
Protecting Critical Section Code on a Pipeline Digital Signal Controller
Started by ●May 17, 2004
