Hello, I'm looking for a method to map some peripheral registers to the last 64 locations in memory. Right now I'm using statements like bfset #PWM_LOAD_OK_BIT_ON_MASK,X:PWMA_PMCTL_ADDR where #define PWMA_PMCTL_ADDR 0x1200 /*PWM Control Register*/ and #define PWM_LOAD_OK_BIT_ON_MASK 0x0002 This instruction takes 6 clocks and 3 words. When using an instruction like bfset #xxxx,X:pp it will take 4 clocks and 2 words. In this case X:pp is somewhere in the last 64 locations in memory. But I do not know how to get used the peripheral register by X:pp. In the manuals there's something written about special kinds of busses which must be implemented on the DSP to be able to use X:pp. But it's not so clear. Does anyone have any ideas ? Thanks and regards, Micheal |
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Register mapping at 56F807
Started by ●October 25, 2002
Reply by ●October 25, 20022002-10-25
The memory addresses of the on-chip peripherals are fixed and cannot be
changed. If you are accessing several peripheral registers in a section of code, you could do something like this: //------------------------------// defines // Offset values for assembler routines (eg interrupts) #define DSPSCI_BR_OFFSET 0 // baud rate register #define DSPSCI_CR_OFFSET 1 // control register #define DSPSCI_SR_OFFSET 2 // status register #define DSPSCI_DR_OFFSET 3 // data register // The Sci0 Uart Address and Registers #define Sci0_Uart_Address ArchIO.Sci0 #define Sci0_BaudRateReg ArchIO.Sci0.BaudRateReg #define Sci0_ControlReg ArchIO.Sci0.ControlReg #define Sci0_StatusReg ArchIO.Sci0.StatusReg #define Sci0_DataReg ArchIO.Sci0.DataReg // The Sci1 Uart Address and Registers #define Sci1_Uart_Address ArchIO.Sci1 #define Sci1_BaudRateReg ArchIO.Sci1.BaudRateReg #define Sci1_ControlReg ArchIO.Sci1.ControlReg #define Sci1_StatusReg ArchIO.Sci1.StatusReg #define Sci1_DataReg ArchIO.Sci1.DataReg //------------------------------// code // r2 points to the SCI move #Sci1_Uart_Address,r2 // Read the SCI status register to clear the interrupt move x:(r2 + DSPSCI_SR_OFFSET),y0 // Write the SCI status register to clear the status bits move y0,x:(r2 + DSPSCI_SR_OFFSET) // Read the received character into y0 move x:(r2 + DSPSCI_DR_OFFSET),y0 The addressing mode "X:(R2+xx)", when used with an internal register as a source or destination, uses 1 word and 4 clock cycles. The same addressing mode, when used with instructions like "bfset" or "bfclr" uses 2 words and 6 clock cycles, so it is not much of a saving in this case. Regards, Art Johnson Senior Systems Analyst PMC Prime Mover Controls Inc. 3600 Gilmore Way Burnaby, B.C., Canada V5G 4R8 Phone: 604 433-4644 FAX: 604 433-5570 Email: http://www.pmc-controls.com -----Original Message----- From: michaelknop [mailto:] Sent: Friday, October 25, 2002 1:34 AM To: Subject: [motoroladsp] Register mapping at 56F807 Hello, I'm looking for a method to map some peripheral registers to the last 64 locations in memory. Right now I'm using statements like bfset #PWM_LOAD_OK_BIT_ON_MASK,X:PWMA_PMCTL_ADDR where #define PWMA_PMCTL_ADDR 0x1200 /*PWM Control Register*/ and #define PWM_LOAD_OK_BIT_ON_MASK 0x0002 This instruction takes 6 clocks and 3 words. When using an instruction like bfset #xxxx,X:pp it will take 4 clocks and 2 words. In this case X:pp is somewhere in the last 64 locations in memory. But I do not know how to get used the peripheral register by X:pp. In the manuals there's something written about special kinds of busses which must be implemented on the DSP to be able to use X:pp. But it's not so clear. Does anyone have any ideas ? Thanks and regards, Micheal _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: To Post: To Leave: Archives: http://www.yahoogroups.com/group/motoroladsp More Groups: http://www.dsprelated.com/groups.php3 ">http://docs.yahoo.com/info/terms/ |
Reply by ●October 25, 20022002-10-25
Looking at Section 3.4 of the DSP56F80x Users Manual,
it describes only 3 "Core Configuration" registers that are available to the
"short" instruction mode. While I am sure that there are others, these
appear to be the only documented ones (Table 3-10).
While the section is confusing, I would interpret it
to mean that even if the EX (external Memory) bit is set, these 3 registers can
still be accessed via the short address mode. I would then interpret that
to mean, that even if you have external memory mapped registers, they cannot be
accessed via the short address mode.
Jerry.
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