Forums

IRQA interrupt handling....; Art Johnson

Started by Nitin Madhukar Yewale November 15, 2002
Hi,
I am using 56F826 for my project. I have configured IRQA
interrupt as edge triggred and it is connected to external ADC. After
EOC (4.1 micro seconds) it will generate interrupt and I will have to
read digital value.

But I can see that IRQA pin is generating interrupt but it is
not going into ISR. So I think the reason for the same is that there
should be a bit which will tell me that IRQA interrupt has occurred and
I will have to clear so that whenever interrupt occurs it will go to
ISR.

Which is the register that will tell me that IRQA interrupt is
pending? Generally clearing of interrupt pending is to be done for Level
sensitive interrupts.
Regards,
Nitin.


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Here is how we set up the IRQA and IRQB interrupts here, and they work OK for
us:

================================

In the file "appconfig.h:

/****************************************************************************
*
* CORE Initialization
*
* (definitions from the SDK file "coredrv.h")
*
****************************************************************************/
/* Bus configuration */

#define BUS_CONTROL_DRV_BIT_0 0x0000
#define BUS_CONTROL_DRV_BIT_1 0x0200

#ifdef EXTRAM_VERSION
#define BUS_CONTROL_EXT_X_MEM_WAIT_STATES 0
#else
#define BUS_CONTROL_EXT_X_MEM_WAIT_STATES 8
#endif
#define BUS_CONTROL_EXT_X_MEM_SLOW_WAIT_STATES 12

#define BUS_CONTROL_EXT_P_MEM_WAIT_STATES 0

#define BUS_CONTROL_REG ( BUS_CONTROL_DRV_BIT_1 \
| (BUS_CONTROL_EXT_X_MEM_WAIT_STATES << 4) \
| BUS_CONTROL_EXT_P_MEM_WAIT_STATES )

#define BUS_CONTROL_REG_SLOW ( BUS_CONTROL_DRV_BIT_1
\
| (BUS_CONTROL_EXT_X_MEM_SLOW_WAIT_STATES << 4)
\
| BUS_CONTROL_EXT_P_MEM_WAIT_STATES
) /* Interrupt Priority configuration */
#define INTERRUPT_PRIORITY_REG ( IPR_ENABLE_CHANNEL_0 \
| IPR_ENABLE_CHANNEL_1 \
| IPR_ENABLE_CHANNEL_2 \
| IPR_ENABLE_CHANNEL_3 \
| IPR_ENABLE_CHANNEL_4 \
| IPR_ENABLE_CHANNEL_5 \
| IPR_ENABLE_CHANNEL_6 \
/* | IPR_ENABLE_IRQA */ \
/* | IPR_ENABLE_IRQB */ \
/* | IPR_IRQA_TRIGGER_HIGH_LEVEL */ \
/* | IPR_IRQB_TRIGGER_HIGH_LEVEL */ ) // IRQA and IRQB must remain disabled until the XR16C2850 DUART
// chip has been initialized and is driving the IRQA and IRQB
// lines to the "inactive" level.
#define IPR_IRQA_ENABLE_BITS ( IPR_ENABLE_IRQA \
| IPR_IRQA_TRIGGER_HIGH_LEVEL )

#define IPR_IRQB_ENABLE_BITS ( IPR_ENABLE_IRQB \
| IPR_IRQB_TRIGGER_HIGH_LEVEL ) // Definitions for the SCI #2 Receive/Transmit interrupt (IRQA),
// which is vector number 8.
//
// These definitions are required so the interrupt vector
// and priority are set by the standard files "vector.c",
// "config.c", and "const.c"
//
#ifndef com2_os_debug
#define GPR_INT_PRIORITY_8 6
#ifdef BYPASS_SDK_INTERRUPT_DSPATCHER
#define INTERRUPT_VECTOR_ADDR_8 Sci2_Task_Rx_Tx_Interrupt
#endif

// Definitions for the SCI #3 Receive/Transmit interrupt (IRQB),
// which is vector number 9.
//
// These definitions are required so the interrupt vector
// and priority are set by the standard files "vector.c",
// "config.c", and "const.c"
//
#ifndef com3_os_debug
#define GPR_INT_PRIORITY_9 6
#ifdef BYPASS_SDK_INTERRUPT_DSPATCHER
#define INTERRUPT_VECTOR_ADDR_9 Sci3_Task_Rx_Tx_Interrupt
#endif ================================

Note that we have NOT enabled IRQA and IRQB yet, because in our system we must
initialize the off-chip peripheral BEFORE we enable IRQA and IRQB. Here is the
code where we do that:

================================

//------------------------------// macros

//
// Macro to enable the SCI2 interrupt (IRQA)
//
#define Sci2_Interrupt_Enable() \
ArchCore.InterruptPriorityReg |= IPR_IRQA_ENABLE_BITS
//
// Macro to enable the SCI3 interrupt (IRQB)
//
#define Sci3_Interrupt_Enable() \
ArchCore.InterruptPriorityReg |= IPR_IRQB_ENABLE_BITS

// In the code, AFTER the SCI2 and SCI3 ports (XR16C2850)
// have been initialized, we do this: //
// Enable the SCI2 interrupt (IRQA), now that the XR16C2850
// INTA output is enabled and is driving the IRQA line to
// the "inactive" level.
//
Sci2_Interrupt_Enable(); //
// Enable the SCI3 interrupt (IRQB), now that the XR16C2850
// INTB output is enabled and is driving the IRQB line to
// the "inactive" level.
//
Sci3_Interrupt_Enable(); ================================ The above code works for us in our 56F807 software, and it should also work in
your 56F826 software. Please let me know if you have any more problems.

Also, Motorola has 2 excellent Application Notes about the ADCs:
AN1933/D "Synchronizing of On-Chip Analog to Digital Converter on DSP56F80x
DSPs"
AN1947/D "DSP56800 ADC"

You can get them at:
http://e-www.motorola.com/brdata/PDFDB/docs/AN1933.pdf
http://e-www.motorola.com/brdata/PDFDB/docs/AN1947.pdf

Motorola has many links to Application Notes for the DSP56F8xx DSP chips, just
go to their website at:
http://e-www.motorola.com/webapp/sps/site/homepage.jsp?nodeIdM0ylgz6wY

Then select the chip you are using (for example, DSP56F826):
- In the Search area (top right) enter DSP56F826 and press Go
- Click on the link to "DSP56F826 Product Summary Page"
- On this page scroll down to "DSP56F826 Documentation"
- You will see a section titled "Application Note", this has links to all the
Application Notes that apply to the DSP56F826 chip.

I hope this helps.

Regards,

Art Johnson
Senior Systems Analyst
PMC Prime Mover Controls Inc.
3600 Gilmore Way
Burnaby, B.C., Canada
V5G 4R8
Phone: 604 433-4644
FAX: 604 433-5570
Email:
http://www.pmc-controls.com
-----Original Message-----
From: Nitin Madhukar Yewale [mailto:]
Sent: Thursday, November 14, 2002 9:57 PM
To:
Cc: Art Johnson
Subject: IRQA interrupt handling....; Art Johnson Hi,
I am using 56F826 for my project. I have configured IRQA
interrupt as edge triggred and it is connected to external ADC. After
EOC (4.1 micro seconds) it will generate interrupt and I will have to
read digital value.

But I can see that IRQA pin is generating interrupt but it is
not going into ISR. So I think the reason for the same is that there
should be a bit which will tell me that IRQA interrupt has occurred and
I will have to clear so that whenever interrupt occurs it will go to
ISR.

Which is the register that will tell me that IRQA interrupt is
pending? Generally clearing of interrupt pending is to be done for Level
sensitive interrupts.
Regards,
Nitin.