Hey guys!

My masters degree thesis is digital lock-in amplifier. I want to make it on an FPGA to learn this piece of hardware. Basically I have a budget of 220€ (260$) but preferably something around 150€.

My friend recommended me some model of Artix (I want Xilinx's component, because when I was flicking through job offers it was the most common one) so I found this: ARTY A7-35T DIGILENT.

Now - the FPGA subject is so broad I probably won't even grasp at the beginning how limiting or how allowing specific parameters of this hardware are. I just want to quickly get started without overheating my head trying to work out which parameters will prove to be problematic with this project.

So my question is - is this FPGA model that I chose suitable for:

- implementing low-pass/high-pass digital filters

- fourier transform

- linear regression to fit sinusoid (let's say 200kHz max) to a signal coming from ADC

- mixing of harmonic waves

- performing all the tasks above parallelly (3 independent... let's call it computing processes because I'm missing a word here)

Additionally:

- digital PLL for a single reference signal

- digital synthesis of sine wave (I was actually thinking about a look-up table solution)

Thank you for your help!

90 DSP48 units of this FPGA are enough to implement a lot of DSP algorithms.

But you would rather implement the filters and FFT in the sequential-parallel manner.

When you will try to do the parallel FIR filter of the order, say 200, for the precise signal filtering, then it would not fit the device.

Corn1996,

You first have to gather some skills in the design of phase lock loops. From your questions I gather you are trying to align the frequency and phase of two periodic oscillators.  This is very different from aligning the carrier of a local oscillator the the frequency of a modulated signal without an embedded carrier of the timing clock of a modulated received signal. It is not hard to these things but you must first master the techniques.  I would start here... read the synch material and ten contact me... fjharris@ucsd.edu

WPMC_2012_BE_synch_camera_ready.pdf

synchronize_L3_2011.doc

Lets_assume_System_synchronized_2.pdf 

fred h

Not really enough information.  Look at the resources on the chip, and guesstimate how many MAC operations per second you need for each of the tasks.  You've got 90 DSP48 units, and attaining a 25MHz clock rate is within reach of a dreadful beginner -- is 225 MAC/us fast enough?  If not, then getting up to about half of what Xilinx claims is the chip's top speed is probably attainable with some flogging.

Depending on what you're doing, it's probably possible to do things like sample at faster than you can process, and chewing through a vector of samples semi-off-line.

I would think that this is suitable. 100's of tap FIR filters can be produced using 10's of DSP blocks. The NCO will probably need 3-5 DSP blocks depending if you add a gain stage. MMCMs provide clock synthesis and are quite flexible.

The key thing is whether the board has a license for the Vivado tool suite and whether this is the webpack or a single year license included. The base tool should have the correct IPs you are looking for, but these would be worth checking before any purchase. 

I'm using the PYNQ-Z2 board to teach Verilog at work.  This board is a smoking deal:

https://www.dfrobot.com/product-1838.html?gclid=Cj...

https://www.newark.com/tul-corporation/1m4-m000127...

https://www.mouser.com/ProductDetail/DFRobot/DFR06...

https://www.digikey.com/en/products/detail/dfrobot...

You *can* use it for the PYNQ platform.  But I've just been using it tethered for vanilla Verilog.  You can also bring it up with using the Zynq just like a Zedboard but for less.  It is much more capable than the Arty-35 for about the same money.  For any of these environments esp. Zynq be prepared to spend time bringing up the system.  At work another engineer helped me get the Zed-board going with the Zynq with system builder *and* he got a command line monitor going.  I don't know if I would have got there by myself.  We also got the system down to where I had a "bucket" into which I could pour all my Verilog code to do DSP.  That took some time.

Best of luck,

Mark Napier

If you have access to xilinx compiler then you can start your coding and finish simulation then compile and see for sure if it fits the target fpga before buying the board.

Regarding fft, filters...etc xilinx provides ips that you can use and design at a click of mouse.

You also need to check what board features you need apart from fpga.

If you are worried about resource then running on a faster clock can allow sharing of resource.

Most modern fpgas have ready made PLL/DPLL blocks

Hm, such questions populate our German electronics forum 3 times a day. I'm far away from wanting to attack anyone, but on the one hand such questions don't really belong in such a forum and on the other hand I wonder how it will be with the young engineers if they don't know and learn the basics of development. Of course you have to do it as described above, so FIRST a resource estimation and THEN a component selection. Whithout this information nobody can recommen anything and it is all about guessing. 

I think it is THAT what should be taught to the students. We were working with digital devices and processors at a time when the tools didn't support that and had to do that though. Is that no longer taught today? That's the key thing about engineering. (?) Defining and translating functions and estimating their computing time requirements. Min-max-analysis, time requirements, real-time issues and all that solidly set up and documented. I see more and more companies, involving unexperienced engineers in these decisions and where exactly this simple rule is violated and whole projects are driven to the wall, because nobody sat down and took 30min time to prepare a ragged Excel sheet. 

Somehow irritating

So much for the "Word on Sunday"

Assuming that your maximum signal frequency will be 200kHz and the sample rate around 1Mhz the Artix 35 FPGA is perfectly capable of realising some kind of digitally implemented lock in filter.

I'm more than little puzzled by your choice of algorithms to implement the system -but that's your problem.

I've implemented a functional 8 channel lock in amplifier in a few thousand LUTs on an Altera MAX10 FPGA using 230kHz sampling rates. It doesn't use Fourier transforms or linear regression. It would have been perfectly feasible to operate at 1MHz sample rates.

The best way to approach this problem is to model the signal processing on some tool which makes no assumptions about hardware, I would use MATLAB and possibly SIMULINK. Once you have done that you will be in a good position to estimate the amount of maths and therefore FPGA fabric and multipliers that you will need.

You could equally well use Python, C or C++ to do the modelling.

Is the PLL required to lock your filter to a reference signal at the operating frequency ? (Some posters have suggested that FPGAs contain PLLs (which is true) but they are for logic clocks but not suitable for your lock in amplifier (its frequency is much too low).

MK