I want to PLL on the line voltage, here in Europe 50Hz. I have a noisy signal and i use a prefilter with a complex pole pair at 0.999*exp(+/- j*2*pi*50/10000). 10ks/s is my sample rate. Not suprisingly the phase response is horrible, 1/2Hz off in frequency the phase is 25° shifted. I cannot tolerate such shifts because it is the phase i need, it should not change that much with frequency change.
Is there a smart trick to mitigate or compensate for the phase shift?
How fast do you want to track the line voltage? Is this single phase or three phase? Do you need an estimate every cycle, or half cycle, or faster (3ph)? These are important aspects of deciding on your trade offs (classic X-Y problem issue).
Over 40 years ago I was looking at a 3ph to 6ph transformer, 6 phase rectified, and a once per cycle (zero crossing) counter on a Voltage to Frequency converter of that rectified signal to get an average voltage per cycle for research into Generator control. The lab computer was a CP1600 Gemini at 1MHz clock using paper tape (sitting in the loft awaiting restoration ;-). DSP has moved on, but the problems stay the same !
THX, yes, the whole plan, ( narrow bandpass, than PLL) is a misconcept. The noise mitigation has to be a part of the PLL. And yes, I want to multiply (mix) incoming sine wave with my local osc. signal.
I am not the first to build a PLL on line freq., I go back to the books and see how the rest of the folks solve it.
>> the filter becomes unstable. <<
No, in that case it does not. But I am aware of the numerical issues close at the unit circle, 32Bit floats may not work. Rough estimate: 12 incoming bits, another 10 Bits from 1/(1-0.999) leaves 10 Bit 'working space'.64 Bit is emulated by the STM32F303, no chance for realtime application.
>> Or try a non-recursive filter, which takes more arithmetic but has zero phase shift. <<
The calculation burden is too high. I alredy had to go down to 10ks/s to stay realtime.
>>How fast do you want to track the line voltage? <<
Hm, as fast as I can. I want to sort events in 512 bins related to the phase of the sine wave. If the freq. is 0.5Hz off, I am ~5 bins off, that is ok.
>> DSP has moved on, but the problems stay the same ! <<
No, problems got worse :).
The amount of 0.999 of the poles causes the poles to be very close to the unit circle in the z complex plane. In implementation, the poles can go outside the unit circle and the filter becomes unstable.
Why have you limited yourself to a complex pole pair? Maybe try a Bessel filter. What bandwidth do you need? How much attenuation can you stand?
Or try a non-recursive filter, which takes more arithmetic but has zero phase shift.