Hi all,

I’m fairly new to DSP and trying to evaluate whether the current filtering solution on our ASIC could be improved. Here’s the setup:

• Modulator: 3rd-order CIFF incremental sigma-delta
• Conversion: fixed time, producing a bitstream of N bits
• Current filtering: 4-section CIC filter with OSR = N/4, followed by "averaging" up to M samples (M input voltages)
• Measurement target: DC voltages
• Bit-rate / effective sampling frequency: 13.1 MHz

Here’s my current understanding and questions:

1. CIC Filter Latency / OSR Limit: I believe the CIC filter has an initial latency before producing steady outputs of OSR * NUMBER of CIC SECTIONS, limiting the maximum OSR to N/4 in my case, is my understanding correct?
2. Effective Decimation: Despite the fact that the OSR is N/4, can the CIC stage be effectively considered as a 4-section CIC filter decimated by M, with an additional down-sampling by 4 because the first three outputs of the CIC filter (after N, 2N, 3N cycles) are discarded?
3. DC-Only Measurement / Multi-Stage Filtering: Since I’m primarily interested in the DC component, is this approach optimal? Would a different multi-stage solution (e.g., CIC + FIR or other) be more efficient? Most references suggest CIC filters are used as first-stage decimators followed by other filtering, but in my case, the limited number of decimated samples may constrain the order of downstream filters.
4. Alternative Averaging Approach: Would it be better for the CIC filter to internally average the M samples instead of resetting the filter for each measurement, compared to the current CIC + M sample averaging approach?

Any insights, references, or suggestions for alternative filtering strategies for DC measurement in this context would be greatly appreciated!

Thanks in advance,

Hello,

I'm trying to understand.  So you have an A to D converter?  Bit compare frequency 13.1 MHz ?

Then a 3rd order noise shaper?

Then a 4 stage CIC decimator ?  Decimation rate?

Lastly an average of M samples?  Is this a box-car recursive moving average or are you effectively down sampling by M at this stage?

What are you trying to optimize? Area, power, noise?

Also, is this a single measurement stream?  

Mark Napier

Hi Mark,
here’s a bit more context so the setup is clearer.

This is an incremental sigma-delta ADC, so the modulator is reset every conversion and produces a fixed-length bitstream. The sigma delta modulator is 3rd order, running at 13.1MHz.

Downstream I have what is effectively a reconstruction filter implemented as a 4-stage CIC (differential delay = 1). The decimation rate R is configurable and it is a by-product of the programmable conversion time, since that determines how many bits the sigma delta modulator generates per conversion.

For example, with ~20 µs conversion time we get ~256 bits (20us*13.1MHz). I choose R as large as possible (so that the CIC "cut-off" frequency is the lowest) assuming that the CIC’s fully settles within those 256 input samples.

Using the CIC impulse response length
  L = N · (R – 1) + 1
with N = 4, I end up with R ≈ 64 as the largest value that fits inside a 256-sample conversion.

The output of the CIC is then accumulated and an average value is generated after M CIC outputs. An important note is that the M samples are consecutive measurements of a stable/very slow (w.r.t the conversion rate) varying quantity.

My goal is to understand whether this CIC-plus-averaging structure is the best way to extract a clean DC estimate from a fixed set of N x M sigma-delta bits, or whether another filtering architecture might provide better noise rejection given these constraints.

Thanks again for helping me reason through it.

Antonio 

OK, now I understand.

What you should look at is the combined response of the two filter stages.  1st is the CIC decimator, 2nd is the response of the single boxcar average.

The CIC will have a step response.  The rise time determined by the frequency roll off in the decimated output.  So the 1st few samples should be discarded as they will skew your average.  I would simulate to get a good picture.  I guess that you are doing some power of 2 length average to simplify the math.

Another thing is that the average is a single boxcar that has a slow roll off with regular stop-band zeros.  If you plot the total CIC roll off with the interpolated boxcar response you can get the combined response of both filters.  This will tell you how far down the noise can be attenuated.

Also consider the output spectrum of the Delta-Sigma converter as it will shape the noise.

The combination of all of these will give you the spectrum of your output noise and so the effective resolution of the DC measurement in terms of equivalent bits.

So back to the question: what is the best way?  Depends on your resources I guess.  The CIC decimator is there to simplify the math for the average.  A no holds barred approach would be a window on all the data.

As for resetting the CIC, it depends.  If the S-D A2D converter runs continuously then the CIC can run continuously after init as well.  That would get rid of the step response samples you need to discard.  How often does your system need the DC measurement?  Is there a power savings requirement?

Mark Napier

With the following

The CIC will have a step response.  The rise time determined by the frequency roll off in the decimated output.  So the 1st few samples should be discarded as they will skew your average.  I would simulate to get a good picture.  I guess that you are doing some power of 2 length average to simplify the math.

You meant that in order to check how many of the initial samples out of my CIC decimator I could simulate the step response of the filter and evaluate how long it takes to the filter to reach a steady state? 

Regarding the combined response of the CIC decimator and the boxcar filter, what I need to do is to interpolate with zeros the impulse response of the boxcar filter such that the b coefficients of the boxcar filter are interleaved with OSR-1 zeros in between. Do the convolution of the filters impulse response and then I can plot the combined frequency response?

Referring to the holds barred approach, what exactly do you mean with a window on all the data? 
I think that in the way I setup my CIC decimator currently, it already holds all the data generated by one conversion right? I like to imaging the 4 stage CIC, as 4 cascaded moving sum filters (boxcar) each with length equal to the CIC OSR and I take one sample out of the cascade of these 4 filters every 4*OSR input samples.
Or did you mean an FIR based solution with 4*OSR taps? Could that theoretically deliver a better noise rejection?

With respect whether I can keep the CIC running or not, in my system the delta-sigma ADC is multiplexed by 2 channels. So measurements of quantity A are interleaved with quantity B and for each measurement the delta-sigma modulator has to be reset. 
Currently in the system there is single CIC decimator and M output are stored (accumulated) for A and B separately.  

What I was thinking of doing is to have 2 CICs one for A and one for B, but keep on pushing the bitstream of the M samples of A and B in their respective CICs and have the CIC to be configured with an OSR M times the original one. So that my system still produces a single decimated value after N*M input bits.



 
Thanks for taking the time to read this!
Antonio