Exploring adders: carry select adder any benefits?
Started by 10 years ago●2 replies●latest reply 10 years ago●480 viewsThis discussion explores the performance benefits of using a Carry-Select Adder (CSA) compared to standard inferred adders across different FPGA technologies. The original poster shares experimental data showing that while CSA can occasionally achieve a higher maximum frequency, it rarely outperforms inferred adders for common bit-widths.
The thread also touches on the differences between FPGA and ASIC implementations, highlighting how routing delays and physical layout impact the effectiveness of various adder architectures.
- Experimental data shows that inferred adders generally outperform carry-select adders on modern FPGAs for standard bit-widths.
- In ASIC design, the overhead of routing signals to and from a CSA may negate the speed gains achieved by bypassing carry chains.
- The effectiveness of a specific adder architecture is highly dependent on the target technology and standard cell libraries used.
- Adders exceeding 64 bits are noted as uncommon in practical applications, making some architectural comparisons academic.
At some point in the past I had used a carry-select-adder to meet timing for a larger adder. I did a little experiment to see how often this is true. The following plot shows the max frequency for three different FPGAs and compares the inferred adder to a carry-select-adder.
The area of interest is typically way to the left, the above is somewhat academic because adders over 64 bits are not that common. There are a couple small regions where the CSA achieved a higher Fmax (max frequency) than the inferred adder but in general not often.
All of this changes when you write code for an Asic. In today's processes you lay out a ripple-carry adder and you minimize the carry chain length by packing it into a tight array. If you try to implement a CSA then you will loose more time routing a signal away from the array and back than you will gain from bypassing big chunks of the carry chain.
@jt_eaton, the above was an experiment with FPGA technologies only, and not an all encompassing experiment (e.g. only a subset of vendors).
Not sure I agree with your arguement for the ASIC though, in a CSA you would still have the tightly packed arrays for the smaller adder blocks and then select from those array. It would be interesting to see similar data for different standard cell libraries.
