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Re: Clock drift and compensation

Reply posted 7 years ago (02/25/2018)
Hi Chalil,Assume my input & output DMA size is 128 samples each, and resampling is happening on input side as well, then if the jitter buffer hit high water...

Re: Clock drift and compensation

Reply posted 7 years ago (02/12/2018)
Hi Chalil,Suppose if I put a timestamp at input side DMA buffer, and try to use that at output side by comparing with the current time, and find the delta between...

Re: Clock drift and compensation

Reply posted 7 years ago (02/06/2018)
Hi Chalil,As you know my primary aim is to apply this on a broadcast receiver where the audio is received on AIR and channel decoder does the demodulation of digital...

Re: Clock drift and compensation

Reply posted 7 years ago (02/05/2018)
Hi Chalil,Thanks for the detailed explanation, I would like to go some more finer details as I think it would be good to discuss. Suppose when it reaches lower/higher...

Re: Clock drift and compensation

Reply posted 7 years ago (02/04/2018)
Hi Chalil,Suppose if I move this to output side, First I wait the jitter buffer to be half fill, ie wait for 5 audio packets which will fill the jitter buffer...

Re: Clock drift and compensation

Reply posted 7 years ago (01/31/2018)
Hi Chalil,Yes, asrc is required but how accuratley estimate the drift and find the src ratio ?-ben

Clock drift and compensation

New thread started 7 years ago
Hi,I have  a system which has a tuner chip and DSP chip, both are clocked by independent xtals. Tuner gives the baseband samples to DSP, and tuner is master and...

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