DSPRelated.com

Mohan Yellayi (@my1958)

ASIC and FPGA designer. Implementing DSP algorithms in FPGA. Worked on various ASIC chips, networking, cell phone handsets, high performance computing. favorite languages - MATLAB, VHDL, Verilog

function [rts1,rts2,coef0,coef1,ff1,ff2]=tonycxx(n_ord,wo,bw,fc,k_ordr, mode)% mode = 1 for lowpass prototype% mode = 2 to bandwidth and center frequency of prototype%...
Here it isfunction tony_des_2(action)% tony_des_2 forms coefficients of two path recursive polyphase filter% filter can be halfband quadrature mirror, polynomials...

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