vlads,
On Sun, Apr 18, 2010 at 6:06 AM, wrote:
> Hi there.
> I'm using C6415 in my circuit with the EMIFA connected to an SDRAM on
CE0
> and an FPGA on CE2 (configured as a programmable synchronous memory), both
> having the same bus width (64 bit).
>
> I was wondering how an EDMA transfer would work between these two spaces.
> Since the bus is shared, I'm guessing that part of the data from the
source
> (or all of it) is stored in the DSP's internal memory first, and then
that
> data would be copied to the destination from the DSP. Or am I mistaken? :)
>
The cycles work basically the same for external-to-external transfers.
The *simplified* description would be-
The internal transfer controller calls for a read cycle[s] to be generated.
The EMIF for the addressed CE space generates a mem read cycle based on its
configuration.
The transfer controller captures the read data and calls for a write
cycle[s] to be generated.
The EMIF for the addressed CE space generates a mem write cycle based on its
configuration.
The transfer count is updated and the cycle repeats until the count is
exhausted.
mikedunn
>
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php