> What did you expect to happen when the execution ran
off
> the end of the program?
Yes I agree, to "exit main" is generally not a good idea in the TI environment.
But it shouldn't cause mysterious
target/emulator errors unless something is wrong with the C$$EXIT vector. As I
recall, in a DSP/BIOS-enabled program,
doing this takes you back to some type of idle loop and DSP/BIOS is no longer
active (at least in the sense of
processing timer ticks). But in either case, the emulator should still work
fine and it should be no problem to see
where you are and what code is executing.
Yi, my suggestion is to keep the while (1) as last line of main() as a
work-around. Like a safety net.
Mike or other TI tools experts on the forum may have some idea of exactly what
is wrong. But in our lab, we would
consider this as "fixed" with a work-around that prevents main() from a final
exit. After all, you can always do a
"Reset CPU" and re-run your code from that point.
-Jeff
> ---------- Original Message -----------
> From: Yi Guo
> To: Jeff Brower , c...
> Sent: Thu, 17 Feb 2011 17:48:52 -0800 (PST)
> Subject: Re: [c6x] problem with using clock() and printf()
>
>> Hi, Jeff,
>> Ok, so you removed clock() and printf() -- as the only changes -- and
>> no error messages?
>> > Yes.
>>
>> The code after being changed:
>> #include
>> #include
>>
>> void main()
>> {
>> int j, a = 0;
>> clock_t start, finish;
>> double duration;
>> start = 1;//clock();
>> for (j = 0; j < 3; j++) {
>> a += 1;
>> }
>> finish = 8;//clock();
>> duration = (double)(finish -start) / CLOCKS_PER_SEC;
>> // printf("%f\n", duration);
>> }
>>
>> In this case you keep clock() and printf(), and add while (1) as last
>> line of code inside main(), and again, no errors?
>> >yes.
>>
>> The code after being changed:
>> #include
>> #include
>>
>> void main()
>> {
>> int j, a = 0;
>> clock_t start, finish;
>> double duration;
>> start = clock();
>> for (j = 0; j < 3; j++) {
>> a += 1;
>> }
>> finish = clock();
>> duration = (double)(finish -start) / CLOCKS_PER_SEC;
>> printf("%f\n", duration);
>> while(1);
>> }
>>
>> ________________________________
>> From: Jeff Brower
>> To: c...
>> Cc: Yi Guo
>> Sent: Fri, February 18, 2011 8:30:05 AM
>> Subject: Re: [c6x] problem with using clock() and printf()
>>
>> Yi Guo-
>>
>> > Thenks. See the Q&As bellow.
>> >
>> > 1) This may have been asked already... did you try without
clock() and
>> > printf()? With those lines commented, do you
>> > still get breakpoint-related error messages?
>> >>no, i don't.
>>
>> Ok, so you removed clock() and printf() -- as the only changes -- and
>> no error messages?
>>
>> > 2) If you add:
>> >
>> > while (1);
>> >
>> > as the last line, can the program run without errors?
>> >> yes, it runs well.
>>
>> In this case you keep clock() and printf(), and add while (1) as last
>> line of code inside main(), and again, no errors?
>>
>> -Jeff
>>
>> > ________________________________
>> > From: Jeff Brower
>> > To: c...
>> > Cc: Yi Guo
>> > Sent: Thu, February 17, 2011 12:44:43 PM
>> > Subject: Re: [c6x] problem with using clock() and printf()
>> >
>> > Yi Guo-
>> >
>> >> void main()
>> >> {
>> >> int j, a = 0;
>> >> clock_t start, finish;
>> >> double duration;
>> >> start = clock();
>> >> for (j = 0; j < 3; j++) {
>> >> a += 1;
>> >> }
>> >> finish = clock();
>> >> duration = (double)(finish -start) / CLOCKS_PER_SEC;
>> >> printf("%f\n", duration);
>> >> }
>> >
>> > 1) This may have been asked already... did you try without clock() and
>> > printf()? With those lines commented, do you
>> > still get breakpoint-related error messages?
>> >
>> > 2) If you add:
>> >
>> > while (1);
>> >
>> > as the last line, can the program run without errors?
>> >
>> > -Jeff
>> >
>> >
>> >> Mikedunn,
>> >>
>> >> Thank you for help.
>> >> I didn't find any optimization options were selected:
>> >> Build option-->compiler-->opt level-->noneBuild
option-->compiler-->program
>> >> level opt-->none
>> >>
>> >> I followed the steps you provided to do some test for some times, I
>> >> always received an error message from CCS:
>> >> Error: Error 0x0000000C/-2044 Error during: Register, Break Point,
No
>> >> breakpoint at 0x00007360
>> >>
>> >> Then here are Q&As.
>> >> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that
results
>> are
>> >> consistent. results??
>> >> See the error message above.
>> >>
>> >> Q2. What are the contents of your GEL file?? paste in your next post.
>> >> /*--------------------------*/
>> >> /* EVMDM642.gel */
>> >> /* Version 1.70 */
>> >> /*--------------------------*/
>> >> /* The StartUp() function is called each time CCS is started. */
>> >> /* Customize this function to perform desired initialization. */
>> >> /*--------------------------*/
>> >> StartUp()
>> >> {
>> >> setup_memory_map();
>> >> GEL_Reset();
>> >> init_emif();
>> >> }
>> >> /*--------------------------*/
>> >> /* Setup memory map for DM642 EVM. */
>> >> /* */
>> >> /*--------------------------*/
>> >> setup_memory_map()
>> >> {
>> >> GEL_MapOn();
>> >> GEL_MapReset();
>> >> /* On-chip memory map */
>> >> GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal
Memory */
>> >> GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL REGS
*/
>> >> GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL
REGS */
>> >> GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL
REGS */
>> >> GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL
REGS */
>> >> GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL
REGS */
>> >> GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL
REGS */
>> >> GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL REGS
*/
>> >> GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND
PARAM */
>> >> GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL
REGS */
>> >> GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL REGS
*/
>> >> GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL
REGS */
>> >> GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO REGS
*/
>> >> GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device
Configuration */
>> >> GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL REGS
*/
>> >> GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL
REGS */
>> >> GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL REGS
*/
>> >> GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM
REGS */
>> >> GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0 Control
*/
>> >> GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1 Control
*/
>> >> GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2 Control
*/
>> >> GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL REGS
*/
>> >> GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC Wrapper
*/
>> >> GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP REGS
*/
>> >> GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL REGS
*/
>> >> GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA REGS
*/
>> >> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data, EDMA
map */
>> >> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data, EDMA
map */
>> >> GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel A
Data */
>> >> GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel B
Data */
>> >> GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel A
Data */
>> >> GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel B
Data */
>> >> GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel A
Data */
>> >> GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel B
Data */
>> >> /* Off-chip memory map */
>> >> GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM EMIF-A,
CE0*/
>> >> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); /* 4MB Flash EMIF-A,
CE1 */
>> >> GEL_MapAdd(0x90080000, 0, 0x00080000, 1, 1); /* 4MB FPGA EMIF-A,
CE1 */
>> >> GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE2
EXPANSION */
>> >> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3
EXPANSION */
>> >> }
>> >> /*--------------------------*/
>> >> /* init_emif() */
>> >> /*--------------------------*/
>> >> init_emif()
>> >> {
>> >> #define EMIFA_GCTL 0x01800000
>> >> #define EMIFA_CE1 0x01800004
>> >> #define EMIFA_CE0 0x01800008
>> >> #define EMIFA_CE2 0x01800010
>> >> #define EMIFA_CE3 0x01800014
>> >> #define EMIFA_SDRAMCTL 0x01800018
>> >> #define EMIFA_SDRAMTIM 0x0180001c
>> >> #define EMIFA_SDRAMEXT 0x01800020
>> >> #define EMIFA_CE1SECCTL 0x01800044
>> >> #define EMIFA_CE0SECCTL 0x01800048
>> >> #define EMIFA_CE2SECCTL 0x01800050
>> >> #define EMIFA_CE3SECCTL 0x01800054
>> >>
>> >> /* EMIFA */
>> >> *(int *)EMIFA_GCTL = 0x00052078;
>> >> *(int *)EMIFA_CE0 = 0xffffffd3; /* CE0 SDRAM */
>> >> *(int *)EMIFA_CE1 = 0x73a28e01; /* CE1 Flash + CPLD
*/
>> >> *(int *)EMIFA_CE2 = 0x22a28a22; /* CE2 Daughtercard
32-bit async */
>> >> *(int *)EMIFA_CE3 = 0x22a28a42; /* CE3 Daughtercard
32-bit sync */
>> >> *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM control
*/
>> >> *(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing
(refresh) */
>> >> *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended
control */
>> >> *(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control
Reg. */
>> >> *(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control
Reg. */
>> >> *(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control
Reg. */
>> >> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary Control
Reg. */
>> >> }
>> >> /*--------------------------*/
>> >> /* clear_memory_map() */
>> >> /*--------------------------*/
>> >> clear_memory_map()
>> >> {
>> >> GEL_MapOff();
>> >> }
>> >> /*--------------------------*/
>> >> /* FlushCache() */
>> >> /*--------------------------*/
>> >> FlushCache()
>> >> {
>> >> /* Invalidate L1I and L1D */
>> >> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
>> >>
>> >> /* Clean L2 */
>> >> *(int *)0x01845004 = 0x1;
>> >> }
>> >>
>> >> /*--------------------------*/
>> >> /* OnReset() */
>> >> /*--------------------------*/
>> >> OnReset(int nErrorCode)
>> >> {
>> >> init_emif();
>> >> }
>> >>
>> >> /*--------------------------*/
>> >> /* OnPreFileLoaded() */
>> >> /* This function is called automatically when the 'Load
Program'*/
>> >> /* Menu item is selected. */
>> >> /*--------------------------*/
>> >> OnPreFileLoaded()
>> >> {
>> >> /* GEL_Reset(); -- Commented out for CCS 2.20 */
>> >> FlushCache();
>> >> IER = 0;
>> >> IFR = 0;
>> >> init_emif();
>> >> }
>> >> /*--------------------------*/
>> >> /* OnRestart() */
>> >> /* This function is called by CCS when you do Debug->Restart. */
>> >> /* The goal is to put the C6x into a known good state with */
>> >> /* respect to cache, edma and interrupts. */
>> >> /* Failure to do this can cause problems when you restart and */
>> >> /* run your application code multiple times. This is different */
>> >> /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
>> >> /* C6x into a known good state. */
>> >> /*--------------------------*/
>> >> OnRestart(int nErrorCode )
>> >> {
>> >> /* Turn off L2 for all EMIFA CE spaces. App should
>> >> * manage these for coherancy in the application.
>> >> * GEL_TextOut("Turn off cache segment\n");
>> >> */
>> >> *(int *)0x1848200 = 0; /* MAR0 */
>> >> *(int *)0x1848204 = 0; /* MAR1 */
>> >> *(int *)0x1848208 = 0; /* MAR2 */
>> >> *(int *)0x184820c = 0; /* MAR3 */
>> >>
>> >> /* Disable EDMA events and interrupts and clear any
>> >> * pending events.
>> >> * GEL_TextOut("Disable EDMA event\n");
>> >> */
>> >> *(int *)0x01A0FFA8 = 0; /* CIERH */
>> >> *(int *)0x01A0FFB4 = 0; /* EERH */
>> >> *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
>> >>
>> >> *(int *)0x01A0FFE8 = 0; /* CIERL */
>> >> *(int *)0x01A0FFF4 = 0; /* EERL */
>> >> *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */
>> >>
>> >> /* Disable other interrupts */
>> >> IER = 0;
>> >> IFR = 0;
>> >> }
>> >> /*--------------------------*/
>> >> /* RESET MENU */
>> >> /*--------------------------*/
>> >> menuitem "Resets";
>> >> hotmenu Reset_BreakPts_and_EMIF()
>> >> {
>> >> GEL_BreakPtReset();
>> >> GEL_Reset();
>> >> init_emif();
>> >> }
>> >> hotmenu Flush_Cache()
>> >> {
>> >> FlushCache();
>> >> }
>> >> /*--------------------------*/
>> >> /* MEMORY MAP MENU */
>> >> /*--------------------------*/
>> >> menuitem "Memory Map";
>> >> hotmenu SetMemoryMap()
>> >> {
>> >> setup_memory_map();
>> >> }
>> >> hotmenu ClearMemoryMap()
>> >> {
>> >> clear_memory_map();
>> >> }
>> >> /*--------------------------*/
>> >> /* BOARD OPTIONS MENU */
>> >> /*--------------------------*/
>> >> menuitem "Board Options";
>> >> #define CPLD_REVISION 0x9008001F
>> >> hotmenu CheckFPGARevision()
>> >> {
>> >> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char
*)CPLD_REVISION);
>> >> GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on
>> >> (DS9)\n","Output",1,1,1);
>> >> }
>> >>
>> >> Q3. What is your target board??
>> >> EVMDM642
>> >> 720MHz
>> >>
>> >> ________________________________
>> >> From: mikedunn
>> >> To: Yi Guo
>> >> Cc: c...
>> >> Sent: Thu, February 17, 2011 3:21:51 AM
>> >> Subject: Re: [c6x] problem with using clock() and printf()
>> >>
>> >>
>> >> Yi Guo,
>> >>
>> >> OK, lets see if we can get a set of consistent symptoms.
>> >> Note that the steps below apply to first and second generation C6000
devices
>> >> [like 6201, 6713, 6416] in addition to the DM642. Do not use with C64+
>> > devices.
>> >> The following steps will are not likely to resolve your problem, but
they
>> will
>> >> eliminate any doubts WRT extraneous interrupts and possible erratic
reset
>> >> behavior. IMO it is always good practice to initialize the interrupt
vectors
>> >> when troubleshooting [I plug them with breakpoints - if you get an
unexpected
>> >> interrupt, you know it right away].
>> >> STEP 1:
>> >> First a minor change to the .cmd file. add the 'VECS' and
'.vectors' lines as
>> >> shown below:
>> >> --begin--
>> >> MEMORY
>> >> {
>> >> VECS: org = 000h, len = 400h
>> >> IRAM: org = 400h, len = 0FC00h
>> >> }
>> >> SECTIONS
>> >> {
>> >> .vectors :> VECS
>> >> ------end of changes---
>> >> STEP 2:
>> >> Then add the code below to a file called 'vectors.asm'.
>> >> Begin 'vectors.asm'---------
>> >> ;
>> >> ; Copyright 2003 by Texas Instruments Incorporated.
>> >> ; All rights reserved. Property of Texas Instruments
Incorporated.
>> >> ; Restricted rights to use, duplicate or disclose this code are
>> >> ; granted through contract.
>> >> ;
>> >> ;
>> >> ; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
>> >> ; hacked by mikedunn
>> >> ;
>> >
>> >
>> >
> ------- End of Original Message -------
_____________________________________
Reply by mikedunn●February 18, 20112011-02-18
Yi Guo,
What version of the CodeGen tools are you using?
mikedunn
On 2/17/2011 10:52 PM, Richard Williams wrote: > Yi Guo,
>
> What did you expect to happen when the execution ran off the end of
> the program?
>
> R. Williams
>
> ---------- Original Message -----------
> From: Yi Guo >
> To: Jeff Brower
> >, c...
>
> Sent: Thu, 17 Feb 2011 17:48:52 -0800 (PST)
> Subject: Re: [c6x] problem with using clock() and printf()
>
> > Hi, Jeff,
> > Ok, so you removed clock() and printf() -- as the only changes -- and
> > no error messages?
> > > Yes.
> >
> > The code after being changed:
> > #include
> > #include
> >
> > void main()
> > {
> > int j, a = 0;
> > clock_t start, finish;
> > double duration;
> > start = 1;//clock();
> > for (j = 0; j < 3; j++) {
> > a += 1;
> > }
> > finish = 8;//clock();
> > duration = (double)(finish -start) / CLOCKS_PER_SEC;
> > // printf("%f\n", duration);
> > }
> >
> > In this case you keep clock() and printf(), and add while (1) as last
> > line of code inside main(), and again, no errors?
> > >yes.
> >
> > The code after being changed:
> > #include
> > #include
> >
> > void main()
> > {
> > int j, a = 0;
> > clock_t start, finish;
> > double duration;
> > start = clock();
> > for (j = 0; j < 3; j++) {
> > a += 1;
> > }
> > finish = clock();
> > duration = (double)(finish -start) / CLOCKS_PER_SEC;
> > printf("%f\n", duration);
> > while(1);
> > }
> >
> > ________________________________
> > From: Jeff Brower
> >
> > To: c...
> > Cc: Yi Guo >
> > Sent: Fri, February 18, 2011 8:30:05 AM
> > Subject: Re: [c6x] problem with using clock() and printf()
> >
> > Yi Guo-
> >
> > > Thenks. See the Q&As bellow.
> > >
> > > 1) This may have been asked already... did you try without
> clock() and
> > > printf()? With those lines commented, do you
> > > still get breakpoint-related error messages?
> > >>no, i don't.
> >
> > Ok, so you removed clock() and printf() -- as the only changes -- and
> > no error messages?
> >
> > > 2) If you add:
> > >
> > > while (1);
> > >
> > > as the last line, can the program run without errors?
> > >> yes, it runs well.
> >
> > In this case you keep clock() and printf(), and add while (1) as last
> > line of code inside main(), and again, no errors?
> >
> > -Jeff
> >
> > > ________________________________
> > > From: Jeff Brower
> >
> > > To: c...
> > > Cc: Yi Guo >
> > > Sent: Thu, February 17, 2011 12:44:43 PM
> > > Subject: Re: [c6x] problem with using clock() and printf()
> > >
> > > Yi Guo-
> > >
> > >> void main()
> > >> {
> > >> int j, a = 0;
> > >> clock_t start, finish;
> > >> double duration;
> > >> start = clock();
> > >> for (j = 0; j < 3; j++) {
> > >> a += 1;
> > >> }
> > >> finish = clock();
> > >> duration = (double)(finish -start) / CLOCKS_PER_SEC;
> > >> printf("%f\n", duration);
> > >> }
> > >
> > > 1) This may have been asked already... did you try without clock() and
> > > printf()? With those lines commented, do you
> > > still get breakpoint-related error messages?
> > >
> > > 2) If you add:
> > >
> > > while (1);
> > >
> > > as the last line, can the program run without errors?
> > >
> > > -Jeff
> > >
> > >
> > >> Mikedunn,
> > >>
> > >> Thank you for help.
> > >> I didn't find any optimization options were selected:
> > >> Build option-->compiler-->opt level-->noneBuild
> option-->compiler-->program
> > >> level opt-->none
> > >>
> > >> I followed the steps you provided to do some test for some times, I
> > >> always received an error message from CCS:
> > >> Error: Error 0x0000000C/-2044 Error during: Register, Break
> Point, No
> > >> breakpoint at 0x00007360
> > >>
> > >> Then here are Q&As.
> > >> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure
> that results
> > are
> > >> consistent. results??
> > >> See the error message above.
> > >>
> > >> Q2. What are the contents of your GEL file?? paste in your next post.
> > >> /*----------------------*/
> > >> /* EVMDM642.gel */
> > >> /* Version 1.70 */
> > >> /*----------------------*/
> > >> /* The StartUp() function is called each time CCS is started. */
> > >> /* Customize this function to perform desired initialization. */
> > >> /*----------------------*/
> > >> StartUp()
> > >> {
> > >> setup_memory_map();
> > >> GEL_Reset();
> > >> init_emif();
> > >> }
> > >> /*----------------------*/
> > >> /* Setup memory map for DM642 EVM. */
> > >> /* */
> > >> /*----------------------*/
> > >> setup_memory_map()
> > >> {
> > >> GEL_MapOn();
> > >> GEL_MapReset();
> > >> /* On-chip memory map */
> > >> GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal Memory */
> > >> GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL REGS */
> > >> GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL REGS */
> > >> GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL REGS */
> > >> GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL REGS */
> > >> GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL REGS */
> > >> GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL REGS */
> > >> GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL REGS */
> > >> GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND
> PARAM */
> > >> GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL REGS */
> > >> GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL REGS */
> > >> GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL REGS */
> > >> GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO REGS */
> > >> GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device
> Configuration */
> > >> GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL REGS */
> > >> GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL REGS */
> > >> GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL REGS */
> > >> GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM REGS */
> > >> GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0 Control */
> > >> GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1 Control */
> > >> GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2 Control */
> > >> GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL REGS */
> > >> GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC Wrapper */
> > >> GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP REGS */
> > >> GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL REGS */
> > >> GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA REGS */
> > >> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data,
> EDMA map */
> > >> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data,
> EDMA map */
> > >> GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel A
> Data */
> > >> GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel B
> Data */
> > >> GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel A
> Data */
> > >> GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel B
> Data */
> > >> GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel A
> Data */
> > >> GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel B
> Data */
> > >> /* Off-chip memory map */
> > >> GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM
> EMIF-A, CE0*/
> > >> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); /* 4MB Flash
> EMIF-A, CE1 */
> > >> GEL_MapAdd(0x90080000, 0, 0x00080000, 1, 1); /* 4MB FPGA EMIF-A,
> CE1 */
> > >> GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE2
> EXPANSION */
> > >> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3
> EXPANSION */
> > >> }
> > >> /*----------------------*/
> > >> /* init_emif() */
> > >> /*----------------------*/
> > >> init_emif()
> > >> {
> > >> #define EMIFA_GCTL 0x01800000
> > >> #define EMIFA_CE1 0x01800004
> > >> #define EMIFA_CE0 0x01800008
> > >> #define EMIFA_CE2 0x01800010
> > >> #define EMIFA_CE3 0x01800014
> > >> #define EMIFA_SDRAMCTL 0x01800018
> > >> #define EMIFA_SDRAMTIM 0x0180001c
> > >> #define EMIFA_SDRAMEXT 0x01800020
> > >> #define EMIFA_CE1SECCTL 0x01800044
> > >> #define EMIFA_CE0SECCTL 0x01800048
> > >> #define EMIFA_CE2SECCTL 0x01800050
> > >> #define EMIFA_CE3SECCTL 0x01800054
> > >>
> > >> /* EMIFA */
> > >> *(int *)EMIFA_GCTL = 0x00052078;
> > >> *(int *)EMIFA_CE0 = 0xffffffd3; /* CE0 SDRAM */
> > >> *(int *)EMIFA_CE1 = 0x73a28e01; /* CE1 Flash + CPLD */
> > >> *(int *)EMIFA_CE2 = 0x22a28a22; /* CE2 Daughtercard 32-bit
> async */
> > >> *(int *)EMIFA_CE3 = 0x22a28a42; /* CE3 Daughtercard 32-bit
> sync */
> > >> *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM control */
> > >> *(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing (refresh)
> */
> > >> *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended control
> */
> > >> *(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control
> Reg. */
> > >> *(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control
> Reg. */
> > >> *(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control
> Reg. */
> > >> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary Control
> Reg. */
> > >> }
> > >> /*----------------------*/
> > >> /* clear_memory_map() */
> > >> /*----------------------*/
> > >> clear_memory_map()
> > >> {
> > >> GEL_MapOff();
> > >> }
> > >> /*----------------------*/
> > >> /* FlushCache() */
> > >> /*----------------------*/
> > >> FlushCache()
> > >> {
> > >> /* Invalidate L1I and L1D */
> > >> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
> > >>
> > >> /* Clean L2 */
> > >> *(int *)0x01845004 = 0x1;
> > >> }
> > >>
> > >> /*----------------------*/
> > >> /* OnReset() */
> > >> /*----------------------*/
> > >> OnReset(int nErrorCode)
> > >> {
> > >> init_emif();
> > >> }
> > >>
> > >> /*----------------------*/
> > >> /* OnPreFileLoaded() */
> > >> /* This function is called automatically when the 'Load
Program'*/
> > >> /* Menu item is selected. */
> > >> /*----------------------*/
> > >> OnPreFileLoaded()
> > >> {
> > >> /* GEL_Reset(); -- Commented out for CCS 2.20 */
> > >> FlushCache();
> > >> IER = 0;
> > >> IFR = 0;
> > >> init_emif();
> > >> }
> > >> /*----------------------*/
> > >> /* OnRestart() */
> > >> /* This function is called by CCS when you do Debug->Restart. */
> > >> /* The goal is to put the C6x into a known good state with */
> > >> /* respect to cache, edma and interrupts. */
> > >> /* Failure to do this can cause problems when you restart and */
> > >> /* run your application code multiple times. This is different */
> > >> /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
> > >> /* C6x into a known good state. */
> > >> /*----------------------*/
> > >> OnRestart(int nErrorCode )
> > >> {
> > >> /* Turn off L2 for all EMIFA CE spaces. App should
> > >> * manage these for coherancy in the application.
> > >> * GEL_TextOut("Turn off cache segment\n");
> > >> */
> > >> *(int *)0x1848200 = 0; /* MAR0 */
> > >> *(int *)0x1848204 = 0; /* MAR1 */
> > >> *(int *)0x1848208 = 0; /* MAR2 */
> > >> *(int *)0x184820c = 0; /* MAR3 */
> > >>
> > >> /* Disable EDMA events and interrupts and clear any
> > >> * pending events.
> > >> * GEL_TextOut("Disable EDMA event\n");
> > >> */
> > >> *(int *)0x01A0FFA8 = 0; /* CIERH */
> > >> *(int *)0x01A0FFB4 = 0; /* EERH */
> > >> *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
> > >>
> > >> *(int *)0x01A0FFE8 = 0; /* CIERL */
> > >> *(int *)0x01A0FFF4 = 0; /* EERL */
> > >> *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */
> > >>
> > >> /* Disable other interrupts */
> > >> IER = 0;
> > >> IFR = 0;
> > >> }
> > >> /*----------------------*/
> > >> /* RESET MENU */
> > >> /*----------------------*/
> > >> menuitem "Resets";
> > >> hotmenu Reset_BreakPts_and_EMIF()
> > >> {
> > >> GEL_BreakPtReset();
> > >> GEL_Reset();
> > >> init_emif();
> > >> }
> > >> hotmenu Flush_Cache()
> > >> {
> > >> FlushCache();
> > >> }
> > >> /*----------------------*/
> > >> /* MEMORY MAP MENU */
> > >> /*----------------------*/
> > >> menuitem "Memory Map";
> > >> hotmenu SetMemoryMap()
> > >> {
> > >> setup_memory_map();
> > >> }
> > >> hotmenu ClearMemoryMap()
> > >> {
> > >> clear_memory_map();
> > >> }
> > >> /*----------------------*/
> > >> /* BOARD OPTIONS MENU */
> > >> /*----------------------*/
> > >> menuitem "Board Options";
> > >> #define CPLD_REVISION 0x9008001F
> > >> hotmenu CheckFPGARevision()
> > >> {
> > >> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char
> *)CPLD_REVISION);
> > >> GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on
> > >> (DS9)\n","Output",1,1,1);
> > >> }
> > >>
> > >> Q3. What is your target board??
> > >> EVMDM642
> > >> 720MHz
> > >>
> > >> ________________________________
> > >> From: mikedunn
> >
> > >> To: Yi Guo >
> > >> Cc: c...
> > >> Sent: Thu, February 17, 2011 3:21:51 AM
> > >> Subject: Re: [c6x] problem with using clock() and printf()
> > >>
> > >>
> > >> Yi Guo,
> > >>
> > >> OK, lets see if we can get a set of consistent symptoms.
> > >> Note that the steps below apply to first and second generation
> C6000 devices
> > >> [like 6201, 6713, 6416] in addition to the DM642. Do not use with
> C64+
> > > devices.
> > >> The following steps will are not likely to resolve your problem,
> but they
> > will
> > >> eliminate any doubts WRT extraneous interrupts and possible
> erratic reset
> > >> behavior. IMO it is always good practice to initialize the
> interrupt vectors
> > >> when troubleshooting [I plug them with breakpoints - if you get
> an unexpected
> > >> interrupt, you know it right away].
> > >> STEP 1:
> > >> First a minor change to the .cmd file. add the 'VECS' and
> '.vectors' lines as
> > >> shown below:
> > >> --begin--
> > >> MEMORY
> > >> {
> > >> VECS: org = 000h, len = 400h
> > >> IRAM: org = 400h, len = 0FC00h
> > >> }
> > >> SECTIONS
> > >> {
> > >> .vectors :> VECS
> > >> ------end of changes---
> > >> STEP 2:
> > >> Then add the code below to a file called 'vectors.asm'.
> > >> Begin 'vectors.asm'---------
> > >> ;
> > >> ; Copyright 2003 by Texas Instruments Incorporated.
> > >> ; All rights reserved. Property of Texas Instruments Incorporated.
> > >> ; Restricted rights to use, duplicate or disclose this code are
> > >> ; granted through contract.
> > >> ;
> > >> ;
> > >> ; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
> > >> ; hacked by mikedunn
> > >> ;
> > >
> > >
> > >
> ------- End of Original Message -------
Reply by Richard Williams●February 18, 20112011-02-18
Yi Guo,
What did you expect to happen when the execution ran off the end of the
program?
R. Williams
---------- Original Message -----------
From: Yi Guo
To: Jeff Brower , c...
Sent: Thu, 17 Feb 2011 17:48:52 -0800 (PST)
Subject: Re: [c6x] problem with using clock() and printf()
> Hi, Jeff,
> Ok, so you removed clock() and printf() -- as the only changes -- and
> no error messages?
> > Yes.
>
> The code after being changed:
> #include
> #include void main()
> {
> int j, a = 0;
> clock_t start, finish;
> double duration;
> start = 1;//clock();
> for (j = 0; j < 3; j++) {
> a += 1;
> }
> finish = 8;//clock();
> duration = (double)(finish -start) / CLOCKS_PER_SEC;
> // printf("%f\n", duration);
> }
>
> In this case you keep clock() and printf(), and add while (1) as last
> line of code inside main(), and again, no errors?
> >yes.
>
> The code after being changed:
> #include
> #include void main()
> {
> int j, a = 0;
> clock_t start, finish;
> double duration;
> start = clock();
> for (j = 0; j < 3; j++) {
> a += 1;
> }
> finish = clock();
> duration = (double)(finish -start) / CLOCKS_PER_SEC;
> printf("%f\n", duration);
> while(1);
> }
>
> ________________________________
> From: Jeff Brower
> To: c...
> Cc: Yi Guo
> Sent: Fri, February 18, 2011 8:30:05 AM
> Subject: Re: [c6x] problem with using clock() and printf()
>
> Yi Guo-
>
> > Thenks. See the Q&As bellow.
> >
> > 1) This may have been asked already... did you try without
clock() and
> > printf()? With those lines commented, do you
> > still get breakpoint-related error messages?
> >>no, i don't.
>
> Ok, so you removed clock() and printf() -- as the only changes -- and
> no error messages?
>
> > 2) If you add:
> >
> > while (1);
> >
> > as the last line, can the program run without errors?
> >> yes, it runs well.
>
> In this case you keep clock() and printf(), and add while (1) as last
> line of code inside main(), and again, no errors?
>
> -Jeff
>
> > ________________________________
> > From: Jeff Brower
> > To: c...
> > Cc: Yi Guo
> > Sent: Thu, February 17, 2011 12:44:43 PM
> > Subject: Re: [c6x] problem with using clock() and printf()
> >
> > Yi Guo-
> >
> >> void main()
> >> {
> >> int j, a = 0;
> >> clock_t start, finish;
> >> double duration;
> >> start = clock();
> >> for (j = 0; j < 3; j++) {
> >> a += 1;
> >> }
> >> finish = clock();
> >> duration = (double)(finish -start) / CLOCKS_PER_SEC;
> >> printf("%f\n", duration);
> >> }
> >
> > 1) This may have been asked already... did you try without clock() and
> > printf()? With those lines commented, do you
> > still get breakpoint-related error messages?
> >
> > 2) If you add:
> >
> > while (1);
> >
> > as the last line, can the program run without errors?
> >
> > -Jeff
> >
> >
> >> Mikedunn,
> >>
> >> Thank you for help.
> >> I didn't find any optimization options were selected:
> >> Build option-->compiler-->opt level-->noneBuild
option-->compiler-->program
> >> level opt-->none
> >>
> >> I followed the steps you provided to do some test for some times, I
> >> always received an error message from CCS:
> >> Error: Error 0x0000000C/-2044 Error during: Register, Break Point,
No
> >> breakpoint at 0x00007360
> >>
> >> Then here are Q&As.
> >> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that results
> are
> >> consistent. results??
> >> See the error message above.
> >>
> >> Q2. What are the contents of your GEL file?? paste in your next post.
> >> /*--------------------------*/
> >> /* EVMDM642.gel */
> >> /* Version 1.70 */
> >> /*--------------------------*/
> >> /* The StartUp() function is called each time CCS is started. */
> >> /* Customize this function to perform desired initialization. */
> >> /*--------------------------*/
> >> StartUp()
> >> {
> >> setup_memory_map();
> >> GEL_Reset();
> >> init_emif();
> >> }
> >> /*--------------------------*/
> >> /* Setup memory map for DM642 EVM. */
> >> /* */
> >> /*--------------------------*/
> >> setup_memory_map()
> >> {
> >> GEL_MapOn();
> >> GEL_MapReset();
> >> /* On-chip memory map */
> >> GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal Memory
*/
> >> GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL REGS
*/
> >> GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL
REGS */
> >> GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL REGS
*/
> >> GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL REGS
*/
> >> GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL REGS
*/
> >> GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL REGS
*/
> >> GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL REGS
*/
> >> GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND
PARAM */
> >> GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL REGS
*/
> >> GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL REGS
*/
> >> GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL REGS
*/
> >> GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO REGS
*/
> >> GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device
Configuration */
> >> GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL REGS
*/
> >> GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL REGS
*/
> >> GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL REGS
*/
> >> GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM REGS
*/
> >> GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0 Control
*/
> >> GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1 Control
*/
> >> GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2 Control
*/
> >> GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL REGS
*/
> >> GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC Wrapper
*/
> >> GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP REGS
*/
> >> GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL REGS
*/
> >> GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA REGS
*/
> >> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data, EDMA map
*/
> >> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data, EDMA map
*/
> >> GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel A
Data */
> >> GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel B
Data */
> >> GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel A
Data */
> >> GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel B
Data */
> >> GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel A
Data */
> >> GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel B
Data */
> >> /* Off-chip memory map */
> >> GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM EMIF-A,
CE0*/
> >> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); /* 4MB Flash EMIF-A, CE1
*/
> >> GEL_MapAdd(0x90080000, 0, 0x00080000, 1, 1); /* 4MB FPGA EMIF-A,
CE1 */
> >> GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE2 EXPANSION
*/
> >> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3 EXPANSION
*/
> >> }
> >> /*--------------------------*/
> >> /* init_emif() */
> >> /*--------------------------*/
> >> init_emif()
> >> {
> >> #define EMIFA_GCTL 0x01800000
> >> #define EMIFA_CE1 0x01800004
> >> #define EMIFA_CE0 0x01800008
> >> #define EMIFA_CE2 0x01800010
> >> #define EMIFA_CE3 0x01800014
> >> #define EMIFA_SDRAMCTL 0x01800018
> >> #define EMIFA_SDRAMTIM 0x0180001c
> >> #define EMIFA_SDRAMEXT 0x01800020
> >> #define EMIFA_CE1SECCTL 0x01800044
> >> #define EMIFA_CE0SECCTL 0x01800048
> >> #define EMIFA_CE2SECCTL 0x01800050
> >> #define EMIFA_CE3SECCTL 0x01800054
> >>
> >> /* EMIFA */
> >> *(int *)EMIFA_GCTL = 0x00052078;
> >> *(int *)EMIFA_CE0 = 0xffffffd3; /* CE0 SDRAM */
> >> *(int *)EMIFA_CE1 = 0x73a28e01; /* CE1 Flash + CPLD */
> >> *(int *)EMIFA_CE2 = 0x22a28a22; /* CE2 Daughtercard
32-bit async */
> >> *(int *)EMIFA_CE3 = 0x22a28a42; /* CE3 Daughtercard
32-bit sync */
> >> *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM control
*/
> >> *(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing
(refresh) */
> >> *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended
control */
> >> *(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control
Reg. */
> >> *(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control
Reg. */
> >> *(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control
Reg. */
> >> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary Control
Reg. */
> >> }
> >> /*--------------------------*/
> >> /* clear_memory_map() */
> >> /*--------------------------*/
> >> clear_memory_map()
> >> {
> >> GEL_MapOff();
> >> }
> >> /*--------------------------*/
> >> /* FlushCache() */
> >> /*--------------------------*/
> >> FlushCache()
> >> {
> >> /* Invalidate L1I and L1D */
> >> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
> >>
> >> /* Clean L2 */
> >> *(int *)0x01845004 = 0x1;
> >> }
> >>
> >> /*--------------------------*/
> >> /* OnReset() */
> >> /*--------------------------*/
> >> OnReset(int nErrorCode)
> >> {
> >> init_emif();
> >> }
> >>
> >> /*--------------------------*/
> >> /* OnPreFileLoaded() */
> >> /* This function is called automatically when the 'Load
Program'*/
> >> /* Menu item is selected. */
> >> /*--------------------------*/
> >> OnPreFileLoaded()
> >> {
> >> /* GEL_Reset(); -- Commented out for CCS 2.20 */
> >> FlushCache();
> >> IER = 0;
> >> IFR = 0;
> >> init_emif();
> >> }
> >> /*--------------------------*/
> >> /* OnRestart() */
> >> /* This function is called by CCS when you do Debug->Restart. */
> >> /* The goal is to put the C6x into a known good state with */
> >> /* respect to cache, edma and interrupts. */
> >> /* Failure to do this can cause problems when you restart and */
> >> /* run your application code multiple times. This is different */
> >> /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
> >> /* C6x into a known good state. */
> >> /*--------------------------*/
> >> OnRestart(int nErrorCode )
> >> {
> >> /* Turn off L2 for all EMIFA CE spaces. App should
> >> * manage these for coherancy in the application.
> >> * GEL_TextOut("Turn off cache segment\n");
> >> */
> >> *(int *)0x1848200 = 0; /* MAR0 */
> >> *(int *)0x1848204 = 0; /* MAR1 */
> >> *(int *)0x1848208 = 0; /* MAR2 */
> >> *(int *)0x184820c = 0; /* MAR3 */
> >>
> >> /* Disable EDMA events and interrupts and clear any
> >> * pending events.
> >> * GEL_TextOut("Disable EDMA event\n");
> >> */
> >> *(int *)0x01A0FFA8 = 0; /* CIERH */
> >> *(int *)0x01A0FFB4 = 0; /* EERH */
> >> *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
> >>
> >> *(int *)0x01A0FFE8 = 0; /* CIERL */
> >> *(int *)0x01A0FFF4 = 0; /* EERL */
> >> *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */
> >>
> >> /* Disable other interrupts */
> >> IER = 0;
> >> IFR = 0;
> >> }
> >> /*--------------------------*/
> >> /* RESET MENU */
> >> /*--------------------------*/
> >> menuitem "Resets";
> >> hotmenu Reset_BreakPts_and_EMIF()
> >> {
> >> GEL_BreakPtReset();
> >> GEL_Reset();
> >> init_emif();
> >> }
> >> hotmenu Flush_Cache()
> >> {
> >> FlushCache();
> >> }
> >> /*--------------------------*/
> >> /* MEMORY MAP MENU */
> >> /*--------------------------*/
> >> menuitem "Memory Map";
> >> hotmenu SetMemoryMap()
> >> {
> >> setup_memory_map();
> >> }
> >> hotmenu ClearMemoryMap()
> >> {
> >> clear_memory_map();
> >> }
> >> /*--------------------------*/
> >> /* BOARD OPTIONS MENU */
> >> /*--------------------------*/
> >> menuitem "Board Options";
> >> #define CPLD_REVISION 0x9008001F
> >> hotmenu CheckFPGARevision()
> >> {
> >> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char
*)CPLD_REVISION);
> >> GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on
> >> (DS9)\n","Output",1,1,1);
> >> }
> >>
> >> Q3. What is your target board??
> >> EVMDM642
> >> 720MHz
> >>
> >> ________________________________
> >> From: mikedunn
> >> To: Yi Guo
> >> Cc: c...
> >> Sent: Thu, February 17, 2011 3:21:51 AM
> >> Subject: Re: [c6x] problem with using clock() and printf()
> >>
> >>
> >> Yi Guo,
> >>
> >> OK, lets see if we can get a set of consistent symptoms.
> >> Note that the steps below apply to first and second generation C6000
devices
> >> [like 6201, 6713, 6416] in addition to the DM642. Do not use with C64+
> > devices.
> >> The following steps will are not likely to resolve your problem, but they
> will
> >> eliminate any doubts WRT extraneous interrupts and possible erratic
reset
> >> behavior. IMO it is always good practice to initialize the interrupt
vectors
> >> when troubleshooting [I plug them with breakpoints - if you get an
unexpected
> >> interrupt, you know it right away].
> >> STEP 1:
> >> First a minor change to the .cmd file. add the 'VECS' and
'.vectors' lines as
> >> shown below:
> >> --begin--
> >> MEMORY
> >> {
> >> VECS: org = 000h, len = 400h
> >> IRAM: org = 400h, len = 0FC00h
> >> }
> >> SECTIONS
> >> {
> >> .vectors :> VECS
> >> ------end of changes---
> >> STEP 2:
> >> Then add the code below to a file called 'vectors.asm'.
> >> Begin 'vectors.asm'---------
> >> ;
> >> ; Copyright 2003 by Texas Instruments Incorporated.
> >> ; All rights reserved. Property of Texas Instruments Incorporated.
> >> ; Restricted rights to use, duplicate or disclose this code are
> >> ; granted through contract.
> >> ;
> >> ;
> >> ; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
> >> ; hacked by mikedunn
> >> ;
> >
> >
> > ------- End of Original Message -------
_____________________________________
Reply by Yi Guo●February 18, 20112011-02-18
Hi, Jeff,
Ok, so you removed clock() and printf() -- as the only changes -- and no error
messages? > Yes.
________________________________
From: Jeff Brower
To: c...
Cc: Yi Guo
Sent: Fri, February 18, 2011 8:30:05 AM
Subject: Re: [c6x] problem with using clock() and printf()
Yi Guo-
> Thenks. See the Q&As bellow.
>
> 1) This may have been asked already... did you try without clock() and
> printf()? With those lines commented, do you
> still get breakpoint-related error messages?
>>no, i don't.
Ok, so you removed clock() and printf() -- as the only changes -- and no error
messages?
> 2) If you add:
>
> while (1);
>
> as the last line, can the program run without errors?
>> yes, it runs well.
In this case you keep clock() and printf(), and add while (1) as last line of
code inside main(), and again, no errors?
-Jeff
> ________________________________
> From: Jeff Brower
> To: c...
> Cc: Yi Guo
> Sent: Thu, February 17, 2011 12:44:43 PM
> Subject: Re: [c6x] problem with using clock() and printf()
>
> Yi Guo-
>
>> void main()
>> {
>> int j, a = 0;
>> clock_t start, finish;
>> double duration;
>> start = clock();
>> for (j = 0; j < 3; j++) {
>> a += 1;
>> }
>> finish = clock();
>> duration = (double)(finish -start) / CLOCKS_PER_SEC;
>> printf("%f\n", duration);
>> }
>
> 1) This may have been asked already... did you try without clock() and
> printf()? With those lines commented, do you
> still get breakpoint-related error messages?
>
> 2) If you add:
>
> while (1);
>
> as the last line, can the program run without errors?
>
> -Jeff
>> Mikedunn,
>>
>> Thank you for help.
>> I didn't find any optimization options were selected:
>> Build option-->compiler-->opt level-->noneBuild
option-->compiler-->program
>> level opt-->none
>>
>> I followed the steps you provided to do some test for some times, I
>> always received an error message from CCS:
>> Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
>> breakpoint at 0x00007360
>>
>> Then here are Q&As.
>> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that results
are >> consistent. results??
>> See the error message above.
>>
>> Q2. What are the contents of your GEL file?? paste in your next post.
>> /*--------------------------*/
>> /* EVMDM642.gel */
>> /* Version 1.70 */
>> /*--------------------------*/
>> /* The StartUp() function is called each time CCS is started. */
>> /* Customize this function to perform desired initialization. */
>> /*--------------------------*/
>> StartUp()
>> {
>> setup_memory_map();
>> GEL_Reset();
>> init_emif();
>> }
>> /*--------------------------*/
>> /* Setup memory map for DM642 EVM. */
>> /* */
>> /*--------------------------*/
>> setup_memory_map()
>> {
>> GEL_MapOn();
>> GEL_MapReset();
>> /* On-chip memory map */
>> GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal Memory */
>> GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL REGS */
>> GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL REGS */
>> GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL REGS */
>> GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL REGS */
>> GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL REGS */
>> GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL REGS */
>> GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL REGS */
>> GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND PARAM */
>> GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL REGS */
>> GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL REGS */
>> GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL REGS */
>> GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO REGS */
>> GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device Configuration */
>> GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL REGS */
>> GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL REGS */
>> GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL REGS */
>> GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM REGS */
>> GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0 Control */
>> GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1 Control */
>> GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2 Control */
>> GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL REGS */
>> GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC Wrapper */
>> GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP REGS */
>> GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL REGS */
>> GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA REGS */
>> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data, EDMA map */
>> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data, EDMA map */
>> GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel A Data */
>> GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel B Data */
>> GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel A Data */
>> GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel B Data */
>> GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel A Data */
>> GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel B Data */
>> /* Off-chip memory map */
>> GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM EMIF-A, CE0*/
>> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); /* 4MB Flash EMIF-A, CE1 */
>> GEL_MapAdd(0x90080000, 0, 0x00080000, 1, 1); /* 4MB FPGA EMIF-A, CE1 */
>> GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE2 EXPANSION */
>> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3 EXPANSION */
>> }
>> /*--------------------------*/
>> /* init_emif() */
>> /*--------------------------*/
>> init_emif()
>> {
>> #define EMIFA_GCTL 0x01800000
>> #define EMIFA_CE1 0x01800004
>> #define EMIFA_CE0 0x01800008
>> #define EMIFA_CE2 0x01800010
>> #define EMIFA_CE3 0x01800014
>> #define EMIFA_SDRAMCTL 0x01800018
>> #define EMIFA_SDRAMTIM 0x0180001c
>> #define EMIFA_SDRAMEXT 0x01800020
>> #define EMIFA_CE1SECCTL 0x01800044
>> #define EMIFA_CE0SECCTL 0x01800048
>> #define EMIFA_CE2SECCTL 0x01800050
>> #define EMIFA_CE3SECCTL 0x01800054
>>
>> /* EMIFA */
>> *(int *)EMIFA_GCTL = 0x00052078;
>> *(int *)EMIFA_CE0 = 0xffffffd3; /* CE0 SDRAM */
>> *(int *)EMIFA_CE1 = 0x73a28e01; /* CE1 Flash + CPLD */
>> *(int *)EMIFA_CE2 = 0x22a28a22; /* CE2 Daughtercard 32-bit async */
>> *(int *)EMIFA_CE3 = 0x22a28a42; /* CE3 Daughtercard 32-bit sync */
>> *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM control */
>> *(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing (refresh) */
>> *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended control */
>> *(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control Reg. */
>> *(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control Reg. */
>> *(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control Reg. */
>> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary Control Reg. */
>> }
>> /*--------------------------*/
>> /* clear_memory_map() */
>> /*--------------------------*/
>> clear_memory_map()
>> {
>> GEL_MapOff();
>> }
>> /*--------------------------*/
>> /* FlushCache() */
>> /*--------------------------*/
>> FlushCache()
>> {
>> /* Invalidate L1I and L1D */
>> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
>>
>> /* Clean L2 */
>> *(int *)0x01845004 = 0x1;
>> }
>>
>> /*--------------------------*/
>> /* OnReset() */
>> /*--------------------------*/
>> OnReset(int nErrorCode)
>> {
>> init_emif();
>> }
>>
>> /*--------------------------*/
>> /* OnPreFileLoaded() */
>> /* This function is called automatically when the 'Load
Program'*/
>> /* Menu item is selected. */
>> /*--------------------------*/
>> OnPreFileLoaded()
>> {
>> /* GEL_Reset(); -- Commented out for CCS 2.20 */
>> FlushCache();
>> IER = 0;
>> IFR = 0;
>> init_emif();
>> }
>> /*--------------------------*/
>> /* OnRestart() */
>> /* This function is called by CCS when you do Debug->Restart. */
>> /* The goal is to put the C6x into a known good state with */
>> /* respect to cache, edma and interrupts. */
>> /* Failure to do this can cause problems when you restart and */
>> /* run your application code multiple times. This is different */
>> /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
>> /* C6x into a known good state. */
>> /*--------------------------*/
>> OnRestart(int nErrorCode )
>> {
>> /* Turn off L2 for all EMIFA CE spaces. App should
>> * manage these for coherancy in the application.
>> * GEL_TextOut("Turn off cache segment\n");
>> */
>> *(int *)0x1848200 = 0; /* MAR0 */
>> *(int *)0x1848204 = 0; /* MAR1 */
>> *(int *)0x1848208 = 0; /* MAR2 */
>> *(int *)0x184820c = 0; /* MAR3 */
>>
>> /* Disable EDMA events and interrupts and clear any
>> * pending events.
>> * GEL_TextOut("Disable EDMA event\n");
>> */
>> *(int *)0x01A0FFA8 = 0; /* CIERH */
>> *(int *)0x01A0FFB4 = 0; /* EERH */
>> *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
>>
>> *(int *)0x01A0FFE8 = 0; /* CIERL */
>> *(int *)0x01A0FFF4 = 0; /* EERL */
>> *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */
>>
>> /* Disable other interrupts */
>> IER = 0;
>> IFR = 0;
>> }
>> /*--------------------------*/
>> /* RESET MENU */
>> /*--------------------------*/
>> menuitem "Resets";
>> hotmenu Reset_BreakPts_and_EMIF()
>> {
>> GEL_BreakPtReset();
>> GEL_Reset();
>> init_emif();
>> }
>> hotmenu Flush_Cache()
>> {
>> FlushCache();
>> }
>> /*--------------------------*/
>> /* MEMORY MAP MENU */
>> /*--------------------------*/
>> menuitem "Memory Map";
>> hotmenu SetMemoryMap()
>> {
>> setup_memory_map();
>> }
>> hotmenu ClearMemoryMap()
>> {
>> clear_memory_map();
>> }
>> /*--------------------------*/
>> /* BOARD OPTIONS MENU */
>> /*--------------------------*/
>> menuitem "Board Options";
>> #define CPLD_REVISION 0x9008001F
>> hotmenu CheckFPGARevision()
>> {
>> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char
*)CPLD_REVISION);
>> GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on
>> (DS9)\n","Output",1,1,1);
>> }
>>
>> Q3. What is your target board??
>> EVMDM642
>> 720MHz
>>
>> ________________________________
>> From: mikedunn
>> To: Yi Guo
>> Cc: c...
>> Sent: Thu, February 17, 2011 3:21:51 AM
>> Subject: Re: [c6x] problem with using clock() and printf()
>> Yi Guo,
>>
>> OK, lets see if we can get a set of consistent symptoms.
>> Note that the steps below apply to first and second generation C6000
devices
>> [like 6201, 6713, 6416] in addition to the DM642. Do not use with C64+
> devices.
>> The following steps will are not likely to resolve your problem, but they will >> eliminate any doubts WRT extraneous interrupts and
possible erratic reset
>> behavior. IMO it is always good practice to initialize the interrupt
vectors
>> when troubleshooting [I plug them with breakpoints - if you get an
unexpected
>> interrupt, you know it right away].
>> STEP 1:
>> First a minor change to the .cmd file. add the 'VECS' and
'.vectors' lines as
>> shown below:
>> --begin--
>> MEMORY
>> {
>> VECS: org = 000h, len = 400h
>> IRAM: org = 400h, len = 0FC00h
>> }
>> SECTIONS
>> {
>> .vectors :> VECS
>> ------end of changes---
>> STEP 2:
>> Then add the code below to a file called 'vectors.asm'.
>> Begin 'vectors.asm'---------
>> ;
>> ; Copyright 2003 by Texas Instruments Incorporated.
>> ; All rights reserved. Property of Texas Instruments Incorporated.
>> ; Restricted rights to use, duplicate or disclose this code are
>> ; granted through contract.
>> ;
>> ;
>> ; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
>> ; hacked by mikedunn
>> ;
>
Reply by Yi Guo●February 18, 20112011-02-18
Mikedunn,
Thanks, see the following Q&As.
Q1. What label is at 0x00007360?? > It's the same point as before. 00007360 C$$EXIT,
abort:
00007360
00000000
NOP
00007364
0001A120
BNOP.S1 0x7364 (PC+4 = 0x00007364),5
00007368
00000000
NOP
0000736C
00000000
NOP
00007370
00000000
NOP
00007374
00000000
NOP
00007378
00000000
NOP
0000737C
00000000 NOP
Q2. When did the error occur?? During program load, go main, or run?? >It occured during run.
Try unloading the GEL file.
Q3. Do you get the same results?? >Yes. (remove the GEL file -> re-compiled the program->
load->go main) 00007360 C$$EXIT,
abort:
00007360
00000000
NOP
00007364
0001A120
BNOP.S1 0x7364 (PC+4 = 0x00007364),5
00007368
00000000
NOP
0000736C
00000000
NOP
00007370
00000000
NOP
00007374
00000000
NOP
00007378
00000000
NOP
0000737C
00000000
NOP
00007380 clock:
00007380
0FFDE010
B.S1 HOSTclock (PC-4352 =
0x00006280)
00007384
00008000
NOP 5
00007388
00000000
NOP
0000738C
00000000
NOP
00007390
00000000
NOP
00007394
00000000
NOP
00007398
00000000
NOP
0000739C
00000000 NOP
If the error is at the clock() BP, change your code to eliminate clock() calls
and replace start and finish with hardcoded values like 1 and 8. Try the 1-4.
Q3. Do you still get an error??
Q4. If yes, what is the error??
Q5. If it is a BP error, what is at that address??
>Since the error is at C$$EXIT, I did not do the things
above.
________________________________
From: mikedunn
To: Yi Guo
Cc: c...
Sent: Thu, February 17, 2011 1:45:20 PM
Subject: Re: [c6x] problem with using clock() and printf()
Yi Guo,
On 2/16/2011 7:05 PM, Yi Guo wrote:
Mikedunn, >
>Thank you for help.
>I didn't find any optimization options were selected:
>Build option-->compiler-->opt level-->noneBuild option-->compiler-->program
>level opt-->none
>
>I followed the steps you provided to do some test for some times, I
>always received an error message from CCS:
>Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
>breakpoint at 0x00007360 You need to give a little help.
Q1. What label is at 0x00007360??
Q2. When did the error occur?? During program load, go main, or run??
Try unloading the GEL file.
Q3. Do you get the same results??
If the error is at the clock() BP, change your code to eliminate clock() calls
and replace start and finish with hardcoded values like 1 and 8. Try the 1-4.
Q3. Do you still get an error??
Q4. If yes, what is the error??
Q5. If it is a BP error, what is at that address??
mikedunn
>Then here are Q&As.
>Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that results are
>consistent. results??
>See the error message above.
>
>Q2. What are the contents of your GEL file?? paste in your next post.
>/*--------------------------*/
>/*
EVMDM642.gel
*/
>/* Version
1.70
*/
>/*--------------------------*/
>/* The StartUp() function is called each time CCS is started. */
>/* Customize this function to perform desired initialization. */
>/*--------------------------*/
>StartUp()
>{
> setup_memory_map();
> GEL_Reset();
> init_emif();
>}
>/*--------------------------*/
>/* Setup memory map for DM642
EVM.
*/
>/*
*/
>/*--------------------------*/
>setup_memory_map()
>{
> GEL_MapOn();
> GEL_MapReset();
> /* On-chip memory map */
> GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal
Memory */
> GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL
REGS */
> GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL
REGS */
> GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL
REGS */
> GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL
REGS */
> GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL
REGS */
> GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL
REGS */
> GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL
REGS */
> GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS
AND PARAM */
> GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL
REGS */
> GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL
REGS */
> GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL
REGS */
> GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO
REGS
*/
> GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device
Configuration */
> GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL
REGS */
> GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL
REGS */
> GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL
REGS */
> GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM
REGS */
> GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0
Control */
> GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1
Control */
> GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2
Control */
> GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL
REGS */
> GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC
Wrapper */
> GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP
REGS */
> GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL
REGS */
> GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA
REGS
*/
> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data,
EDMA map */
> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data,
EDMA map */
> GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel
A Data */
> GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel
B Data */
> GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel
A Data */
> GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel
B Data */
> GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel
A Data */
> GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel
B Data */
> /* Off-chip memory map */
> GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM
EMIF-A, CE0*/
> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); /* 4MB Flash
EMIF-A, CE1 */
> GEL_MapAdd(0x90080000, 0, 0x00080000, 1, 1); /* 4MB FPGA
EMIF-A, CE1 */
> GEL_MapAdd(0xA0000000, 0,
0x10000000, 1, 1); /* EMIF-A, CE2 EXPANSION */
> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3
EXPANSION */
>}
>/*--------------------------*/
>/* init_emif()
*/
>/*--------------------------*/
>init_emif()
>{
>#define EMIFA_GCTL 0x01800000
>#define EMIFA_CE1 0x01800004
>#define EMIFA_CE0 0x01800008
>#define EMIFA_CE2 0x01800010
>#define EMIFA_CE3 0x01800014
>#define EMIFA_SDRAMCTL 0x01800018
>#define EMIFA_SDRAMTIM 0x0180001c
>#define EMIFA_SDRAMEXT 0x01800020
>#define EMIFA_CE1SECCTL 0x01800044
>#define EMIFA_CE0SECCTL 0x01800048
>#define EMIFA_CE2SECCTL 0x01800050
>#define EMIFA_CE3SECCTL 0x01800054
>
> /* EMIFA */
> *(int *)EMIFA_GCTL = 0x00052078;
> *(int *)EMIFA_CE0 =
0xffffffd3; /* CE0
SDRAM
*/
> *(int *)EMIFA_CE1 =
0x73a28e01; /* CE1 Flash +
CPLD
*/
> *(int *)EMIFA_CE2 =
0x22a28a22; /* CE2 Daughtercard 32-bit async */
> *(int *)EMIFA_CE3 =
0x22a28a42; /* CE3 Daughtercard 32-bit sync */
> *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM
control
*/
> *(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing
(refresh) */
> *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended
control */
> *(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary
Control Reg. */
> *(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary
Control Reg. */
> *(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary
Control Reg. */
> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary
Control Reg. */
>}
>/*--------------------------*/
>/*
clear_memory_map()
*/
>/*--------------------------*/
>clear_memory_map()
>{
> GEL_MapOff();
>}
>/*--------------------------*/
>/*
FlushCache()
*/
>/*--------------------------*/
>FlushCache()
>{
> /* Invalidate L1I and L1D */
> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
>
> /* Clean L2 */
> *(int *)0x01845004 = 0x1;
>}
>
>/*--------------------------*/
>/*
OnReset()
*/
>/*--------------------------*/
>OnReset(int nErrorCode)
>{
> init_emif();
>}
>
>/*--------------------------*/
>/*
OnPreFileLoaded()
*/
>/* This function is called automatically when the 'Load Program'*/
>/* Menu item is
selected.
*/
>/*--------------------------*/
>OnPreFileLoaded()
>{
>/* GEL_Reset(); -- Commented out for CCS 2.20 */
> FlushCache();
> IER = 0;
> IFR = 0;
> init_emif();
>}
>/*--------------------------*/
>/*
OnRestart()
*/
>/* This function is called by CCS when you do Debug->Restart. */
>/* The goal is to put the C6x into a known good state
with */
>/* respect to cache, edma and
interrupts.
*/
>/* Failure to do this can cause problems when you restart and */
>/* run your application code multiple times. This is different */
>/* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
>/* C6x into a known good
state.
*/
>/*--------------------------*/
>OnRestart(int nErrorCode )
>{
> /* Turn off L2 for all EMIFA CE spaces.
App should
> * manage these for coherancy in the
application.
> * GEL_TextOut("Turn off cache
segment\n");
> */
> *(int *)0x1848200 = 0; /* MAR0 */
> *(int *)0x1848204 = 0; /* MAR1 */
> *(int *)0x1848208 = 0; /* MAR2 */
> *(int *)0x184820c = 0; /* MAR3 */
>
> /* Disable EDMA events and interrupts and clear
any
> * pending events.
> * GEL_TextOut("Disable EDMA
event\n");
>
*/
> *(int *)0x01A0FFA8 =
0; /* CIERH
*/
> *(int *)0x01A0FFB4 =
0; /* EERH */
> *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
>
> *(int *)0x01A0FFE8 =
0; /* CIERL
*/
> *(int *)0x01A0FFF4 =
0; /* EERL */
> *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */
>
> /* Disable other interrupts */
> IER = 0;
> IFR = 0;
>}
>/*--------------------------*/
>/* RESET
MENU
*/
>/*--------------------------*/
>menuitem "Resets";
>hotmenu Reset_BreakPts_and_EMIF()
>{
> GEL_BreakPtReset();
> GEL_Reset();
> init_emif();
>}
>hotmenu Flush_Cache()
>{
> FlushCache();
>}
>/*--------------------------*/
>/* MEMORY MAP
MENU
*/
>/*--------------------------*/
>menuitem "Memory Map";
>hotmenu SetMemoryMap()
>{
> setup_memory_map();
>}
>hotmenu ClearMemoryMap()
>{
> clear_memory_map();
>}
>/*--------------------------*/
>/* BOARD OPTIONS
MENU
*/
>/*--------------------------*/
>menuitem "Board Options";
>#define CPLD_REVISION 0x9008001F
>hotmenu CheckFPGARevision()
>{
> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char
*)CPLD_REVISION);
> GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on
>(DS9)\n","Output",1,1,1);
>}
>
>Q3. What is your target board??
>EVMDM642
>
>Q4. What is the CPU clock rate??
>720MHz ________________________________
From: mikedunn >To: Yi Guo
>Cc: c...
>Sent: Thu, February 17, 2011 3:21:51 AM
>Subject: Re: [c6x] problem with using clock() and printf()
>
>
>Yi Guo,
>
>OK, lets see if we can get a set of consistent symptoms.
>Note that the steps below apply to first and second generation C6000 devices
>[like 6201, 6713, 6416] in addition to the DM642. Do not use with C64+
devices.
>The following steps will are not likely to resolve your problem, but they will
>eliminate any doubts WRT extraneous interrupts and possible erratic reset
>behavior. IMO it is always good practice to initialize the interrupt vectors
>when troubleshooting [I plug them with breakpoints - if you get an unexpected
>interrupt, you know it right away].
>STEP 1:
>First a minor change to the .cmd file. add the 'VECS' and
'.vectors' lines as
>shown below:
>--begin--
>MEMORY
>{
> VECS: org = 000h, len = 400h
> IRAM: org = 400h, len = 0FC00h
>}
>SECTIONS
>{
> .vectors :> VECS
>------end of changes---
>STEP 2:
>Then add the code below to a file called 'vectors.asm'.
>Begin 'vectors.asm'---------
>;
>; Copyright 2003 by Texas Instruments Incorporated.
>; All rights reserved. Property of Texas Instruments Incorporated.
>; Restricted rights to use, duplicate or disclose this code are
>; granted through contract.
>;
>;
>; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
>; hacked by mikedunn
>;
>
>unused .macro id
>
> .global unused:id:
>unused:id:
> nop
> nop
> .word 0x10000000
;breakpoint opcode
> nop
> nop
> nop
> nop
> nop
>
> .endm
>
> .sect ".vectors"
>
> .ref
_c_int00 ; C
entry point
> .def RESET
; reset vector
> .align
32*8*4 ; must be aligned
on 256 word boundary
>
>RESET:
; reset vector
> mvkl
_c_int00,b0 ; load destination
function address to b0
> mvkh _c_int00,b0
> b
b0
; start branch to destination function
>
nop
>
nop
>
nop
> nop
> nop
>
> ;
> ; plug unused interrupts with
breakpoints to
> ; catch stray interrupts
> ;
> unused 1
> unused 2
> unused 3
> unused 4
> unused 5
> unused 6
> unused 7
> unused 8
> unused 9
> unused 10
> unused 11
> unused 12
> unused 13
> unused 14
> unused 15
>
>End 'vectors.asm'---------
>STEP 3:
>The above changes will do 2 things - reserve the 1k boot area [not so important
>in this case] and plug all of the default interrupt vectors [except for reset]
>with breakpoints. There will be a branch to the C program entry point [c_int00]
>at the reset vector. Change your CCS build options by adding 'RESET'
to the text
>box at:
>'Project->BuildOptions->Linker->CodeEntryPoint'
>
>note: You will get a warning when you rebuild.
>>> warning: entry point other than _c_int00 specified
>[I have no idea why the warning - the reset vector entry point is the correct
>entry point for an embedded application]
>
>When you load the program, the 'green arrow' in the disassembly
window should
>point to the address 0.
>
>Now we are ready to test. Do not get caught up with 'trying to get it to
run'.
>Your goal when you have a problem is to establish a repeatable 'first
failure'.
>0. Make sure that your project is built with the debug option - no optimization
>[thanx for the reminder Richard - bad assumption on my part]
>1. Power up the target and connect CCS.
>2. Load the program - Do not do a CPU reset.
>3. Do a debug->Go main.
>4. Run the target.
>Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that results are
>consistent. results??
>Q2. What are the contents of your GEL file?? paste in your next post.
>Q3. What is your target board??
>Q4. What is the CPU clock rate??
>
>mikedunn
>
>On 2/15/2011 7:30 PM, Yi Guo wrote:
>Mikedunn and Jeff,
>>
>>I'm sorry I snipped the message. Thank you for helping me.
>>Step 1:
>>1, I compile the program.
>>2, reset the CPU by DEBUG-->RESET CPU.
>>3, load the program.
>>At this time, everything looks good. 4. Run. CCS issue an error: Error:
Error
>>0x0000000C/-2044 Error during: Register, Break Point, No breakpoint at
>>0x00006F00. At this moment I can't halt the program.
>>Step 2:
>>I repet 2 and 3 of Step 1, at this time, CCS gives the following message.
>>Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
>>breakpoint at 0x00006F00
>>
>>Trouble Removing Breakpoint with the Action "Terminate Program Execution" at
>>0x6f00: Error 0x00000008/-1076 Error during: Break Point, Cannot
set/verify
>>breakpoint at 0x00006F00
>>There was a suprise, I don't whether this is solution to the problem. I
changed
>>the stack size from 400h to 500 h, there were no errors, and it halted
at a s/w
>>breakpoint if I run the program. Some information from disassembly window is
>>shown as bellow.
>>00006F00 abort,
C$$EXIT:
>>00006F00
00000000
NOP
>>00006F04
0001A120
BNOP.S1 0x6F04 (PC+4 = 0x00006f04),5
>>00006F08
00000000
NOP
>>00006F0C
00000000
NOP
>>00006F10
00000000
NOP
>>00006F14
00000000
NOP
>>00006F18
00000000
NOP
>>00006F1C
00000000 NOP
>>
>>Here are the answers to your questions.
>>
>>Q1. What is your emulator's manufacturer name and model number??
>>> XDS 510, USB2.0 TI dsp emulator.
>>
>>Do the following with CCS up:
>>1. reset the DSP
>>2. load the program. I assume that you will get a failure at 0x00006F60.
>>3. open the disassembly window if it is not open.
>>4. goto address 0x00006000 and highlight from there to 0x000070000. right
click
>>the highlighted block, select copy. then paste it into your reply.
>>>00006F00 abort,
C$$EXIT:
>>00006F00
00000000
NOP
>>00006F04
0001A120
BNOP.S1 0x6F04 (PC+4 = 0x00006f04),5
>>00006F08
00000000
NOP
>>00006F0C
00000000
NOP
>>00006F10
00000000
NOP
>>00006F14
00000000
NOP
>>00006F18
00000000
NOP
>>00006F1C
00000000
NOP
>>00006F20 clock:
>>00006F20
0FFDD010
B.S1 HOSTclock (PC-4480 =
0x00005da0)
>>00006F24
00008000
NOP 5
>>00006F28
00000000
NOP
>>00006F2C
00000000
NOP
>>00006F30
00000000
NOP
>>00006F34
00000000
NOP
>>00006F38
00000000
NOP
>>00006F3C
00000000
NOP
>>00006F40 remove:
>>00006F40
0FFF8810
B.S1 unlink (PC-960 =
0x00006b80)
>>00006F44
00008000
NOP 5
>>00006F48
00000000
NOP
>>00006F4C
00000000
NOP
>>00006F50
00000000
NOP
>>00006F54
00000000
NOP
>>00006F58
00000000
NOP
>>00006F5C
00000000
NOP
>>00006F60 etext, __etext,
_stack:
>>00006F60
00000001
NOP
>>00006F64 00000000 ||
NOP
>>00006F68 30303030 [!B0]
MPY2.M1X A1,B12,A1:A0
>>00006F6C 30303030 [!B0]
MPY2.M1X A1,B12,A1:A0
>>00006F70
00000030
MPY2.M1 A0,A0,A1:A0
>>00006F74
00000000
NOP
>>00006F78
00000000
NOP
>>00006F7C
00000000
NOP
>>00006F80 222834E6 [ B0]
LDW.D2T2 *B10--[1],B4
>>00006F84
00004000
NOP 3
>>00006F88
022808F0
OR.D1 0,A10,A4
>>00006F8C
00100362
B.S2 B4
>>00006F90
01858162
ADDKPC.S2 0x6F94 (PC+20 = 0x00006f94),B3,4
>>00006F94
002C29C0
SUB.D1 A11,0x1,A0
>>00006F98 C0000110 [ A0]
B.S1 0x6F88 (PC+8 =
0x00006f88)
>>00006F9C
05AC29C1
SUB.D1 A11,0x1,A11
>>00006FA0 C22834E6 || [ A0] LDW.D2T2
*B10--[1],B4
>>00006FA4 D205B26E [!A0]
LDW.D2T2 *+B14[1458],B4
>>00006FA8
00004000
NOP 3
>>00006FAC
022808F0
OR.D1 0,A10,A4
>>00006FB0
00002000
NOP 2
>>00006FB4
021042E6
LDW.D2T2 *+B4[2],B4
>>00006FB8
00006000
NOP 4
>>00006FBC
00100362
B.S2 B4
>>00006FC0
02878E6E
LDW.D2T2 *+B14[1934],B5
>>00006FC4
00002000
NOP 2
>>00006FC8
020ECC2A
MVK.S2 0x1d98,B4
>>00006FCC
02388842
ADD.D2 DP,B4,B4
>>00006FD0
021488C2
SUB.D2 B5,B4,B4
>>00006FD4
02104DA2
SHR.S2 B4,0x2,B4
>>00006FD8
00100ADA
CMPLT.L2 0,B4,B0
>>00006FDC 30000D90 [!B0]
B.S1 0x702C (PC+108 =
0x0000702c)
>>00006FE0
053C94F6
STW.D2T2 B10,*SP--[4]
>>00006FE4
053C23C4
STDW.D2T1 A11:A10,*+SP[1]
>>00006FE8
051006A1
OR.S1 0,A4,A10
>>00006FEC 0517805B ||
SUB.L2 B5,4,B10
>>00006FF0 068C06A3 ||
OR.S2 0,B3,B13
>>00006FF4 06BC22F7 ||
STW.D2T2 B13,*+SP[1]
>>00006FF8 059018F0 ||
OR.D1X 0,B4,A11
>>00006FFC 3205B26E [!B0]
LDW.D2T2 *+B14[1458],B4
>>00007000
00000000
NOP
>>
>>5. open a memory window at 0x00006F60.
>>6. open a second memory window at 0x00046F60. I'm not sure if this will
>>work-some c6x devices will 'mirror' the memory contents of internal
memory. If
>>this works, I expect all locations to be the same EXCEPT for 0x00006F60 &
>>0x00046F60. If this is true, copy the contents of 0x00046F60 and paste in your
>>reply.
>>>
>>0x00006F00 abort, C$$EXIT
>>0x00006F00 0x00000000 0x0001A120
>>0x00006F08 0x00000000 0x00000000
>>0x00006F10 0x00000000 0x00000000
>>0x00006F18 0x00000000 0x00000000
>>0x00006F20 clock
>>0x00006F20 0x0FFDD010 0x00008000
>>0x00006F28 0x00000000 0x00000000
>>0x00046F00 -------- --------
>>0x00046F08 -------- --------
>>0x00046F10 -------- --------
>>0x00046F18 -------- --------
>>0x00046F20 -------- --------
>>0x00046F28 -------- --------
>>0x00046F30 -------- --------
>> ________________________________
From: mikedunn >>To: u...@yahoo.com
>>Cc: c...
>>Sent: Wed, February 16, 2011 7:35:58 AM
>>Subject: Re: [c6x] problem with using clock() and printf()
>>
>>unicogse and OTHERS,
>>
>>Do NOT snip messages if you want assistance. It is important to maintain the
>>history. I deal in several problems a day and I cannot remember details about
>>each one - also, there are others who may have missed the original message.
Some
>>of us are very busy professionals who donate time to HELP EVERYONE LEARN and
we
>>do not have time to go back and research the history. I took the time to write
>>this so that it can be a learning experience for you and others.
>>
>>Please see my comments inline below.
>>
>>mikedunn
>>
>>On 2/14/2011 12:44 AM, mikedunn wrote:
>>unicogse,
>>>
>>>On 2/13/2011 8:41 PM, u...@yahoo.com wrote:
>>>
>>>>Hi,all,
>>>>when use the following .cmd and .c files, and load the generated .out file,
I
>>>>encountered an error:
>>>>"Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
>>>>breakpoint at 0x00006F60
>>>>Trouble Removing Breakpoint with the Action "Terminate Program Execution" at
>>>>0x6f60: Error 0x00000008/-1076 Error during: Break Point, Cannot set/verify
>>>>breakpoint at 0x00006F60"
>>>> A few possibilities...
Your target is broken, CCS is not configured correctly, or your project is not
set up correctly. The following questions should help sort it out.
Q1. Have you compiled, loaded, and run a program correctly using this
target and emulator?? >yes
Q2. Does your project include rts6400.lib??
Check CCS 'Option->Customize->Program/Project/CIO' tab. >yes, I did.
Q3. Is 'Do not Set CIO Breakpoint at Load' checked?? [it should NOT
be] >No.
Q4. Is 'Do Not Set End of Program Breakpoint at Load' checked?? [it
should NOT be] >No.
Q5. Is 'Disable All Breakpoints When Loading New Programs' checked??
[it
should NOT be] >No.
Open a memory window in CCS at location 0x00006F60 while connected to
the target.
Change the contents to 0xAAAAAAAA and refresh the window.
Q6. Does the window show 0xAAAAAAAA?? >yes
Change the contents to 0x55555555 and refresh the window.
Q7. Does the window show 0x55555555?? >yes
This tells me that you hardware and emulator appear to be working. Your original
error message indicates that there was problems setting or clearing a
breakpoint. The simple exercise of reading and writing memory proved that it can
be done [setting a sw breakpoint [BP] involves reading a memory location, saving
the value, and writing a BP opcode into the memory location. The issue is
compounded by CCS "helping you" when memory is displayed. If a location is known
to have a BP, CCS shows you the original location contents instead of the actual
location contents.
My gut feeling is that there is a basic mistake that is being missed
somewhere.
Q1. What is your emulator's manufacturer name and model number??
Do the following with CCS up:
1. reset the DSP
2. load the program. I assume that you will get a failure at 0x00006F60.
3. open the disassembly window if it is not open.
4. goto address 0x00006000 and highlight from there to 0x000070000. right click
the highlighted block, select copy. then paste it into your reply.
5. open a memory window at 0x00006F60.
6. open a second memory window at 0x00046F60. I'm not sure if this will
work-some c6x devices will 'mirror' the memory contents of internal
memory. If
this works, I expect all locations to be the same EXCEPT for 0x00006F60 &
0x00046F60. If this is true, copy the contents of 0x00046F60 and paste in your
reply.
mikedunn >FYI-
>The timing info will be misleading on an embedded system.
>stdio on TI's embedded devices works something like this for each stdio
function
>[printf, time, etc]:
>1. A hidden BP is set using special label when the program is loaded.
>2. When the program is run, it halts at the BP.
>3. CCS polls the target for run or halt. If the program is halted, CCS checks
>the label in the symbol table.
>4. If it is a stdio BP, CCS will read memory - I think it is the first add
after
>the BP. The add contains an opcode that indicates the course of action.
>5 Once CCS 'does its duty' according to the opcode, a run command is
issued to
>the target.
>All of this makes stdio very s-l-o-w.
>
>mikedunn
>>If the program runs, it can't go to the end. This problem has confused me
for
>>days. Any hints are welcome. Thank you in advance.
>>
>>Evironment:
>>DM642, CCS3.3
>>
>>CODE:
>>main.cmd
>>MEMORY
>>{
>>IRAM: org = 0h, len = 10000h
>>}
>>
>>SECTIONS
>>{
>>.data :> IRAM
>>.text :> IRAM
>>.switch :> IRAM
>>.stack :> IRAM
>>.bss :> IRAM
>>.cinit :> IRAM
>>.far :> IRAM
>>.cio :> IRAM
>>.const :> IRAM
>>.sysmem :> IRAM
>>.tables :> IRAM
>>}
>>
>>main.c
>>
>>#include
>>#include
>>
>>void main()
>>{
>>int j, a = 0;
>>clock_t start, finish;
>>double duration;
>>start = clock();
>>for (j = 0; j < 3; j++) {
>>a += 1;
>>}
>>finish = clock();
>>duration = (double)(finish -start) / CLOCKS_PER_SEC;
>>printf("%f\n", duration);
>>}
>>
Reply by Yi Guo●February 18, 20112011-02-18
Jeff,
Thenks. See the Q&As bellow.
1) This may have been asked already... did you try without clock() and
printf()? With those lines commented, do you
still get breakpoint-related error messages? >no, i don't.
2) If you add:
while (1);
as the last line, can the program run without errors? > yes, it runs well.
________________________________
From: Jeff Brower
To: c...
Cc: Yi Guo
Sent: Thu, February 17, 2011 12:44:43 PM
Subject: Re: [c6x] problem with using clock() and printf()
1) This may have been asked already... did you try without clock() and
printf()? With those lines commented, do you
still get breakpoint-related error messages?
2) If you add:
while (1);
as the last line, can the program run without errors?
-Jeff > Mikedunn,
>
> Thank you for help.
> I didn't find any optimization options were selected:
> Build option-->compiler-->opt level-->noneBuild option-->compiler-->program
> level opt-->none
>
> I followed the steps you provided to do some test for some times, I
> always received an error message from CCS:
> Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
> breakpoint at 0x00007360
>
> Then here are Q&As.
> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that results
are
> consistent. results??
> See the error message above.
>
> Q2. What are the contents of your GEL file?? paste in your next post.
> /*--------------------------*/
> /* EVMDM642.gel */
> /* Version 1.70 */
> /*--------------------------*/
> /* The StartUp() function is called each time CCS is started. */
> /* Customize this function to perform desired initialization. */
> /*--------------------------*/
> StartUp()
> {
> setup_memory_map();
> GEL_Reset();
> init_emif();
> }
> /*--------------------------*/
> /* Setup memory map for DM642 EVM. */
> /* */
> /*--------------------------*/
> setup_memory_map()
> {
> GEL_MapOn();
> GEL_MapReset();
> /* On-chip memory map */
> GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal Memory */
> GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL REGS */
> GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL REGS */
> GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL REGS */
> GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL REGS */
> GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL REGS */
> GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL REGS */
> GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL REGS */
> GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND PARAM */
> GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL REGS */
> GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL REGS */
> GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL REGS */
> GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO REGS */
> GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device Configuration */
> GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL REGS */
> GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL REGS */
> GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL REGS */
> GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM REGS */
> GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0 Control */
> GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1 Control */
> GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2 Control */
> GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL REGS */
> GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC Wrapper */
> GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP REGS */
> GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL REGS */
> GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA REGS */
> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data, EDMA map */
> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data, EDMA map */
> GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel A Data */
> GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel B Data */
> GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel A Data */
> GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel B Data */
> GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel A Data */
> GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel B Data */
> /* Off-chip memory map */
> GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM EMIF-A, CE0*/
> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); /* 4MB Flash EMIF-A, CE1 */
> GEL_MapAdd(0x90080000, 0, 0x00080000, 1, 1); /* 4MB FPGA EMIF-A, CE1 */
> GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE2 EXPANSION */
> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3 EXPANSION */
> }
> /*--------------------------*/
> /* init_emif() */
> /*--------------------------*/
> init_emif()
> {
> #define EMIFA_GCTL 0x01800000
> #define EMIFA_CE1 0x01800004
> #define EMIFA_CE0 0x01800008
> #define EMIFA_CE2 0x01800010
> #define EMIFA_CE3 0x01800014
> #define EMIFA_SDRAMCTL 0x01800018
> #define EMIFA_SDRAMTIM 0x0180001c
> #define EMIFA_SDRAMEXT 0x01800020
> #define EMIFA_CE1SECCTL 0x01800044
> #define EMIFA_CE0SECCTL 0x01800048
> #define EMIFA_CE2SECCTL 0x01800050
> #define EMIFA_CE3SECCTL 0x01800054
>
> /* EMIFA */
> *(int *)EMIFA_GCTL = 0x00052078;
> *(int *)EMIFA_CE0 = 0xffffffd3; /* CE0 SDRAM */
> *(int *)EMIFA_CE1 = 0x73a28e01; /* CE1 Flash + CPLD */
> *(int *)EMIFA_CE2 = 0x22a28a22; /* CE2 Daughtercard 32-bit async */
> *(int *)EMIFA_CE3 = 0x22a28a42; /* CE3 Daughtercard 32-bit sync */
> *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM control */
> *(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing (refresh) */
> *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended control */
> *(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control Reg. */
> *(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control Reg. */
> *(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control Reg. */
> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary Control Reg. */
> }
> /*--------------------------*/
> /* clear_memory_map() */
> /*--------------------------*/
> clear_memory_map()
> {
> GEL_MapOff();
> }
> /*--------------------------*/
> /* FlushCache() */
> /*--------------------------*/
> FlushCache()
> {
> /* Invalidate L1I and L1D */
> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
>
> /* Clean L2 */
> *(int *)0x01845004 = 0x1;
> }
>
> /*--------------------------*/
> /* OnReset() */
> /*--------------------------*/
> OnReset(int nErrorCode)
> {
> init_emif();
> }
>
> /*--------------------------*/
> /* OnPreFileLoaded() */
> /* This function is called automatically when the 'Load
Program'*/
> /* Menu item is selected. */
> /*--------------------------*/
> OnPreFileLoaded()
> {
> /* GEL_Reset(); -- Commented out for CCS 2.20 */
> FlushCache();
> IER = 0;
> IFR = 0;
> init_emif();
> }
> /*--------------------------*/
> /* OnRestart() */
> /* This function is called by CCS when you do Debug->Restart. */
> /* The goal is to put the C6x into a known good state with */
> /* respect to cache, edma and interrupts. */
> /* Failure to do this can cause problems when you restart and */
> /* run your application code multiple times. This is different */
> /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
> /* C6x into a known good state. */
> /*--------------------------*/
> OnRestart(int nErrorCode )
> {
> /* Turn off L2 for all EMIFA CE spaces. App should
> * manage these for coherancy in the application.
> * GEL_TextOut("Turn off cache segment\n");
> */
> *(int *)0x1848200 = 0; /* MAR0 */
> *(int *)0x1848204 = 0; /* MAR1 */
> *(int *)0x1848208 = 0; /* MAR2 */
> *(int *)0x184820c = 0; /* MAR3 */
>
> /* Disable EDMA events and interrupts and clear any
> * pending events.
> * GEL_TextOut("Disable EDMA event\n");
> */
> *(int *)0x01A0FFA8 = 0; /* CIERH */
> *(int *)0x01A0FFB4 = 0; /* EERH */
> *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
>
> *(int *)0x01A0FFE8 = 0; /* CIERL */
> *(int *)0x01A0FFF4 = 0; /* EERL */
> *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */
>
> /* Disable other interrupts */
> IER = 0;
> IFR = 0;
> }
> /*--------------------------*/
> /* RESET MENU */
> /*--------------------------*/
> menuitem "Resets";
> hotmenu Reset_BreakPts_and_EMIF()
> {
> GEL_BreakPtReset();
> GEL_Reset();
> init_emif();
> }
> hotmenu Flush_Cache()
> {
> FlushCache();
> }
> /*--------------------------*/
> /* MEMORY MAP MENU */
> /*--------------------------*/
> menuitem "Memory Map";
> hotmenu SetMemoryMap()
> {
> setup_memory_map();
> }
> hotmenu ClearMemoryMap()
> {
> clear_memory_map();
> }
> /*--------------------------*/
> /* BOARD OPTIONS MENU */
> /*--------------------------*/
> menuitem "Board Options";
> #define CPLD_REVISION 0x9008001F
> hotmenu CheckFPGARevision()
> {
> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char *)CPLD_REVISION);
> GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on
> (DS9)\n","Output",1,1,1);
> }
>
> Q3. What is your target board??
> EVMDM642
> 720MHz
>
> ________________________________
> From: mikedunn
> To: Yi Guo
> Cc: c...
> Sent: Thu, February 17, 2011 3:21:51 AM
> Subject: Re: [c6x] problem with using clock() and printf()
> Yi Guo,
>
> OK, lets see if we can get a set of consistent symptoms.
> Note that the steps below apply to first and second generation C6000
devices
> [like 6201, 6713, 6416] in addition to the DM642. Do not use with C64+ devices. > The following steps will are not likely to resolve
your problem, but they will
> eliminate any doubts WRT extraneous interrupts and possible erratic reset
> behavior. IMO it is always good practice to initialize the interrupt
vectors
> when troubleshooting [I plug them with breakpoints - if you get an
unexpected
> interrupt, you know it right away].
> STEP 1:
> First a minor change to the .cmd file. add the 'VECS' and
'.vectors' lines as
> shown below:
> --begin--
> MEMORY
> {
> VECS: org = 000h, len = 400h
> IRAM: org = 400h, len = 0FC00h
> }
> SECTIONS
> {
> .vectors :> VECS
> ------end of changes---
> STEP 2:
> Then add the code below to a file called 'vectors.asm'.
> Begin 'vectors.asm'---------
> ;
> ; Copyright 2003 by Texas Instruments Incorporated.
> ; All rights reserved. Property of Texas Instruments Incorporated.
> ; Restricted rights to use, duplicate or disclose this code are
> ; granted through contract.
> ;
> ;
> ; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
> ; hacked by mikedunn
> ;
Reply by Jeff Brower●February 17, 20112011-02-17
Yi Guo-
> Thenks. See the Q&As bellow.
>
> 1) This may have been asked already... did you try without clock() and
> printf()? With those lines commented, do you
> still get breakpoint-related error messages?
>>no, i don't.
Ok, so you removed clock() and printf() -- as the only changes -- and no error
messages?
> 2) If you add:
>
> while (1);
>
> as the last line, can the program run without errors?
>> yes, it runs well.
In this case you keep clock() and printf(), and add while (1) as last line of
code inside main(), and again, no errors?
-Jeff
> ________________________________
> From: Jeff Brower
> To: c...
> Cc: Yi Guo
> Sent: Thu, February 17, 2011 12:44:43 PM
> Subject: Re: [c6x] problem with using clock() and printf()
>
> Yi Guo-
>
>> void main()
>> {
>> int j, a = 0;
>> clock_t start, finish;
>> double duration;
>> start = clock();
>> for (j = 0; j < 3; j++) {
>> a += 1;
>> }
>> finish = clock();
>> duration = (double)(finish -start) / CLOCKS_PER_SEC;
>> printf("%f\n", duration);
>> }
>
> 1) This may have been asked already... did you try without clock() and
> printf()? With those lines commented, do you
> still get breakpoint-related error messages?
>
> 2) If you add:
>
> while (1);
>
> as the last line, can the program run without errors?
>
> -Jeff
>> Mikedunn,
>>
>> Thank you for help.
>> I didn't find any optimization options were selected:
>> Build option-->compiler-->opt level-->noneBuild
option-->compiler-->program
>> level opt-->none
>>
>> I followed the steps you provided to do some test for some times, I
>> always received an error message from CCS:
>> Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
>> breakpoint at 0x00007360
>>
>> Then here are Q&As.
>> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that results
are
>> consistent. results??
>> See the error message above.
>>
>> Q2. What are the contents of your GEL file?? paste in your next post.
>> /*--------------------------*/
>> /* EVMDM642.gel */
>> /* Version 1.70 */
>> /*--------------------------*/
>> /* The StartUp() function is called each time CCS is started. */
>> /* Customize this function to perform desired initialization. */
>> /*--------------------------*/
>> StartUp()
>> {
>> setup_memory_map();
>> GEL_Reset();
>> init_emif();
>> }
>> /*--------------------------*/
>> /* Setup memory map for DM642 EVM. */
>> /* */
>> /*--------------------------*/
>> setup_memory_map()
>> {
>> GEL_MapOn();
>> GEL_MapReset();
>> /* On-chip memory map */
>> GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal Memory */
>> GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL REGS */
>> GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL REGS */
>> GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL REGS */
>> GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL REGS */
>> GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL REGS */
>> GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL REGS */
>> GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL REGS */
>> GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND PARAM */
>> GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL REGS */
>> GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL REGS */
>> GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL REGS */
>> GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO REGS */
>> GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device Configuration */
>> GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL REGS */
>> GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL REGS */
>> GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL REGS */
>> GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM REGS */
>> GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0 Control */
>> GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1 Control */
>> GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2 Control */
>> GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL REGS */
>> GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC Wrapper */
>> GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP REGS */
>> GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL REGS */
>> GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA REGS */
>> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data, EDMA map */
>> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data, EDMA map */
>> GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel A Data */
>> GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel B Data */
>> GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel A Data */
>> GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel B Data */
>> GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel A Data */
>> GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel B Data */
>> /* Off-chip memory map */
>> GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM EMIF-A, CE0*/
>> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); /* 4MB Flash EMIF-A, CE1 */
>> GEL_MapAdd(0x90080000, 0, 0x00080000, 1, 1); /* 4MB FPGA EMIF-A, CE1 */
>> GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE2 EXPANSION */
>> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3 EXPANSION */
>> }
>> /*--------------------------*/
>> /* init_emif() */
>> /*--------------------------*/
>> init_emif()
>> {
>> #define EMIFA_GCTL 0x01800000
>> #define EMIFA_CE1 0x01800004
>> #define EMIFA_CE0 0x01800008
>> #define EMIFA_CE2 0x01800010
>> #define EMIFA_CE3 0x01800014
>> #define EMIFA_SDRAMCTL 0x01800018
>> #define EMIFA_SDRAMTIM 0x0180001c
>> #define EMIFA_SDRAMEXT 0x01800020
>> #define EMIFA_CE1SECCTL 0x01800044
>> #define EMIFA_CE0SECCTL 0x01800048
>> #define EMIFA_CE2SECCTL 0x01800050
>> #define EMIFA_CE3SECCTL 0x01800054
>>
>> /* EMIFA */
>> *(int *)EMIFA_GCTL = 0x00052078;
>> *(int *)EMIFA_CE0 = 0xffffffd3; /* CE0 SDRAM */
>> *(int *)EMIFA_CE1 = 0x73a28e01; /* CE1 Flash + CPLD */
>> *(int *)EMIFA_CE2 = 0x22a28a22; /* CE2 Daughtercard 32-bit async */
>> *(int *)EMIFA_CE3 = 0x22a28a42; /* CE3 Daughtercard 32-bit sync */
>> *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM control */
>> *(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing (refresh) */
>> *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended control */
>> *(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control Reg. */
>> *(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control Reg. */
>> *(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control Reg. */
>> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary Control Reg. */
>> }
>> /*--------------------------*/
>> /* clear_memory_map() */
>> /*--------------------------*/
>> clear_memory_map()
>> {
>> GEL_MapOff();
>> }
>> /*--------------------------*/
>> /* FlushCache() */
>> /*--------------------------*/
>> FlushCache()
>> {
>> /* Invalidate L1I and L1D */
>> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
>>
>> /* Clean L2 */
>> *(int *)0x01845004 = 0x1;
>> }
>>
>> /*--------------------------*/
>> /* OnReset() */
>> /*--------------------------*/
>> OnReset(int nErrorCode)
>> {
>> init_emif();
>> }
>>
>> /*--------------------------*/
>> /* OnPreFileLoaded() */
>> /* This function is called automatically when the 'Load
Program'*/
>> /* Menu item is selected. */
>> /*--------------------------*/
>> OnPreFileLoaded()
>> {
>> /* GEL_Reset(); -- Commented out for CCS 2.20 */
>> FlushCache();
>> IER = 0;
>> IFR = 0;
>> init_emif();
>> }
>> /*--------------------------*/
>> /* OnRestart() */
>> /* This function is called by CCS when you do Debug->Restart. */
>> /* The goal is to put the C6x into a known good state with */
>> /* respect to cache, edma and interrupts. */
>> /* Failure to do this can cause problems when you restart and */
>> /* run your application code multiple times. This is different */
>> /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
>> /* C6x into a known good state. */
>> /*--------------------------*/
>> OnRestart(int nErrorCode )
>> {
>> /* Turn off L2 for all EMIFA CE spaces. App should
>> * manage these for coherancy in the application.
>> * GEL_TextOut("Turn off cache segment\n");
>> */
>> *(int *)0x1848200 = 0; /* MAR0 */
>> *(int *)0x1848204 = 0; /* MAR1 */
>> *(int *)0x1848208 = 0; /* MAR2 */
>> *(int *)0x184820c = 0; /* MAR3 */
>>
>> /* Disable EDMA events and interrupts and clear any
>> * pending events.
>> * GEL_TextOut("Disable EDMA event\n");
>> */
>> *(int *)0x01A0FFA8 = 0; /* CIERH */
>> *(int *)0x01A0FFB4 = 0; /* EERH */
>> *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
>>
>> *(int *)0x01A0FFE8 = 0; /* CIERL */
>> *(int *)0x01A0FFF4 = 0; /* EERL */
>> *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */
>>
>> /* Disable other interrupts */
>> IER = 0;
>> IFR = 0;
>> }
>> /*--------------------------*/
>> /* RESET MENU */
>> /*--------------------------*/
>> menuitem "Resets";
>> hotmenu Reset_BreakPts_and_EMIF()
>> {
>> GEL_BreakPtReset();
>> GEL_Reset();
>> init_emif();
>> }
>> hotmenu Flush_Cache()
>> {
>> FlushCache();
>> }
>> /*--------------------------*/
>> /* MEMORY MAP MENU */
>> /*--------------------------*/
>> menuitem "Memory Map";
>> hotmenu SetMemoryMap()
>> {
>> setup_memory_map();
>> }
>> hotmenu ClearMemoryMap()
>> {
>> clear_memory_map();
>> }
>> /*--------------------------*/
>> /* BOARD OPTIONS MENU */
>> /*--------------------------*/
>> menuitem "Board Options";
>> #define CPLD_REVISION 0x9008001F
>> hotmenu CheckFPGARevision()
>> {
>> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char
*)CPLD_REVISION);
>> GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on
>> (DS9)\n","Output",1,1,1);
>> }
>>
>> Q3. What is your target board??
>> EVMDM642
>> 720MHz
>>
>> ________________________________
>> From: mikedunn
>> To: Yi Guo
>> Cc: c...
>> Sent: Thu, February 17, 2011 3:21:51 AM
>> Subject: Re: [c6x] problem with using clock() and printf()
>> Yi Guo,
>>
>> OK, lets see if we can get a set of consistent symptoms.
>> Note that the steps below apply to first and second generation C6000
devices
>> [like 6201, 6713, 6416] in addition to the DM642. Do not use with C64+
> devices.
>> The following steps will are not likely to resolve your problem, but they
will
>> eliminate any doubts WRT extraneous interrupts and possible erratic reset
>> behavior. IMO it is always good practice to initialize the interrupt
vectors
>> when troubleshooting [I plug them with breakpoints - if you get an
unexpected
>> interrupt, you know it right away].
>> STEP 1:
>> First a minor change to the .cmd file. add the 'VECS' and
'.vectors' lines as
>> shown below:
>> --begin--
>> MEMORY
>> {
>> VECS: org = 000h, len = 400h
>> IRAM: org = 400h, len = 0FC00h
>> }
>> SECTIONS
>> {
>> .vectors :> VECS
>> ------end of changes---
>> STEP 2:
>> Then add the code below to a file called 'vectors.asm'.
>> Begin 'vectors.asm'---------
>> ;
>> ; Copyright 2003 by Texas Instruments Incorporated.
>> ; All rights reserved. Property of Texas Instruments Incorporated.
>> ; Restricted rights to use, duplicate or disclose this code are
>> ; granted through contract.
>> ;
>> ;
>> ; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
>> ; hacked by mikedunn
>> ;
>
_____________________________________
Reply by Richard Williams●February 17, 20112011-02-17
Yi Guo,
So you single stepped the program from reset until near the end of the
program,
where a call is made to printf()
Then (and only then) the code goes into the weeds.
Hummmm.....
Is the library that contains the code for printf() actually linked?
Is the library for the correct Endian mode?
Can you post the relevant portions of the .map file?
R. Williams
---------- Original Message -----------
From: Yi Guo
To: Richard Williams
Cc: c...
Sent: Wed, 16 Feb 2011 17:44:13 -0800 (PST)
Subject: Re: [c6x] problem with using clock() and printf()
> Williams,
>
> Q: does the project have any optimization turned on in the compiler/linker?
> sequence.
> >No.
>
> In a prior post, I ask if you have single stepped through the program
> to determine when/where the instruction pointer steps into the weeds.
> have you done that operation?
> >yes, I did. The only thing I knew is that the error message is saying it
can't
> >set a breakpoint for printf() at the point C$$EXIT.
>
> ________________________________
> From: Richard Williams
> To: u...@yahoo.com
> Cc: c...
> Sent: Wed, February 16, 2011 10:20:42 AM
> Subject: Re: [c6x] problem with using clock() and printf()
>
>
>
> Unicogse,
>
> Q: does the project have any optimization turned on in the compiler/linker?
> sequence.
>
> If optimization is turned on...
> Then the declaration of 'a' and the line a += 1;
> will be eliminated due to 'a' not being used after the loop
> Then the loop will be empty
> Then the loop may (depending on the optimization level) be eliminated.
> Then the code is
> call clock twice in a row
> take the difference between the two calls (which may be 0 or very
> close to 0) Then divide that very small number by a relatively large
> number CLOCK_PER_SECOND
>
> The result may be unprintable with your current %f format factor.
> It seems that any of these factors could result in the program
> initiating a math exception (and the resulting interrupt being
> executed) Your code has no interrupt event handler for the indicated
interrupt.
> All the above is just a guess, but is worth giving some thought toward.
>
> In a prior post, I ask if you have single stepped through the program
> to determine when/where the instruction pointer steps into the weeds.
> have you done that operation?
>
> R. Williams
>
> ---------- Original Message -----------
> From: mikedunn
> To: u...@yahoo.com
> Cc: c...
> Sent: Tue, 15 Feb 2011 17:35:58 -0600
> Subject: Re: [c6x] problem with using clock() and printf()
>
> > unicogse and OTHERS,
> >
> > Do NOT snip messages if you want assistance. It is important to
> > maintain the history. I deal in several problems a day and I cannot
> > remember details about each one - also, there are others who may have
> > missed the original message. Some of us are very busy professionals
> > who donate time to HELP EVERYONE LEARN and we do not have time to go
> > back and research the history. I took the time to write this so that
> > it can be a learning experience for you and others.
> >
> > Please see my comments inline below.
> >
> > mikedunn
> >
> > On 2/14/2011 12:44 AM, mikedunn wrote:
> > > unicogse,
> > >
> > > On 2/13/2011 8:41 PM, u...@yahoo.com wrote:
> > >>
> > >> Hi,all,
> > >> when use the following .cmd and .c files, and load the generated .out
> > >> file, I encountered an error:
> > >> "Error: Error 0x0000000C/-2044 Error during: Register, Break Point,
> > >> No breakpoint at 0x00006F60
> > >> Trouble Removing Breakpoint with the Action "Terminate Program
> > >> Execution" at 0x6f60: Error 0x00000008/-1076 Error during: Break
> > >> Point, Cannot set/verify breakpoint at 0x00006F60"
> > >>
> > >
> > > A few possibilities...
> > > Your target is broken, CCS is not configured correctly, or your
> > > project is not set up correctly. The following questions should help
> > > sort it out.
> > > Q1. Have you compiled, loaded, and run a program correctly using this
> > > target and emulator??
> > > >yes
> > >
> > > Q2. Does your project include rts6400.lib??
> > > Check CCS 'Option->Customize->Program/Project/CIO' tab.
> > > >yes, I did.
> > >
> > > Q3. Is 'Do not Set CIO Breakpoint at Load' checked?? [it should
NOT be]
> > > >No.
> > >
> > > Q4. Is 'Do Not Set End of Program Breakpoint at Load' checked??
[it
> > > should NOT be]
> > > >No.
> > >
> > > Q5. Is 'Disable All Breakpoints When Loading New Programs'
checked?? [it
> > > should NOT be]
> > > >No.
> > >
> > > Open a memory window in CCS at location 0x00006F60 while connected to
> > > the target.
> > > Change the contents to 0xAAAAAAAA and refresh the window.
> > > Q6. Does the window show 0xAAAAAAAA??
> > > >yes
> > >
> > > Change the contents to 0x55555555 and refresh the window.
> > > Q7. Does the window show 0x55555555??
> > > >yes
> >
> > This tells me that you hardware and emulator appear to be working.
> > Your original error message indicates that there was problems setting
> > or clearing a breakpoint. The simple exercise of reading and writing
> > memory proved that it can be done [setting a sw breakpoint [BP]
> > involves reading a memory location, saving the value, and writing a BP
> > opcode into the memory location. The issue is compounded by CCS
> > "helping you" when memory is displayed. If a location is known to have
> > a BP, CCS shows you the original location contents instead of the
> > actual location contents. My gut feeling is that there is a basic
> > mistake that is being missed somewhere. Q1. What is your emulator's
> > manufacturer name and model number?? Do the following with CCS up:
> > 1. reset the DSP
> > 2. load the program. I assume that you will get a failure at 0x00006F60.
> > 3. open the disassembly window if it is not open.
> > 4. goto address 0x00006000 and highlight from there to 0x000070000.
> > right click the highlighted block, select copy. then paste it into
> > your reply.
> > 5. open a memory window at 0x00006F60.
> > 6. open a second memory window at 0x00046F60. I'm not sure if this
> > will work-some c6x devices will 'mirror' the memory contents of
> > internal memory. If this works, I expect all locations to be the same
> > EXCEPT for 0x00006F60 & 0x00046F60. If this is true, copy the contents
> > of 0x00046F60 and paste in your reply.
> >
> > mikedunn
> > >
> > > FYI-
> > > The timing info will be misleading on an embedded system.
> > > stdio on TI's embedded devices works something like this for each
> > > stdio function [printf, time, etc]:
> > > 1. A hidden BP is set using special label when the program is loaded.
> > > 2. When the program is run, it halts at the BP.
> > > 3. CCS polls the target for run or halt. If the program is halted, CCS
> > > checks the label in the symbol table.
> > > 4. If it is a stdio BP, CCS will read memory - I think it is the first
> > > add after the BP. The add contains an opcode that indicates the course
> > > of action.
> > > 5 Once CCS 'does its duty' according to the opcode, a run
command is
> > > issued to the target.
> > > All of this makes stdio very s-l-o-w.
> > >
> > > mikedunn
> > >
> > >
> > >>
> > >> If the program runs, it can't go to the end. This problem has
> > >> confused me for days. Any hints are welcome. Thank you in advance.
> > >>
> > >> Evironment:
> > >> DM642, CCS3.3
> > >>
> > >> CODE:
> > >> main.cmd
> > >> MEMORY
> > >> {
> > >> IRAM: org = 0h, len = 10000h
> > >> }
> > >>
> > >> SECTIONS
> > >> {
> > >> .data :> IRAM
> > >> .text :> IRAM
> > >> .switch :> IRAM
> > >> .stack :> IRAM
> > >> .bss :> IRAM
> > >> .cinit :> IRAM
> > >> .far :> IRAM
> > >> .cio :> IRAM
> > >> .const :> IRAM
> > >> .sysmem :> IRAM
> > >> .tables :> IRAM
> > >> }
> > >>
> > >> main.c
> > >>
> > >> #include
> > >> #include
> > >>
> > >> void main()
> > >> {
> > >> int j, a = 0;
> > >> clock_t start, finish;
> > >> double duration;
> > >> start = clock();
> > >> for (j = 0; j < 3; j++) {
> > >> a += 1;
> > >> }
> > >> finish = clock();
> > >> duration = (double)(finish -start) / CLOCKS_PER_SEC;
> > >> printf("%f\n", duration);
> > >> }
> > >>
> > >>
> ------- End of Original Message -------
> uni ------- End of Original Message -------
_____________________________________
Reply by Richard Williams●February 17, 20112011-02-17
Yi Guo,
When you did the 'run to main', did the code ever get to main()?
BTW:
have you single stepped the code to see where the problem occurs?
All your posts indicate your hitting 'run to main' or 'run'
or something similar.
Until you have single stepped the code from reset, it will be very difficult
to
know what the cause of the problem is.
BTW:
according to your .map file, what is located at the address where the latest
problem is occurring I.E. at 0x7360?
The program halts at 0x7360, have you checked the stack to determine what the
program came from to get to 0x7360?
R. Williams
---------- Original Message -----------
From: Yi Guo
To: mikedunn
Cc: c...
Sent: Wed, 16 Feb 2011 17:05:42 -0800 (PST)
Subject: Re: [c6x] problem with using clock() and printf()
> Mikedunn,
>
> Thank you for help.
> I didn't find any optimization options were selected:
> Build option-->compiler-->opt level-->noneBuild option-->compiler--
> >program level opt-->none I followed the steps you provided to do
> some test for some times, I always received an error message
from CCS:
> Error: Error 0x0000000C/-2044 Error during: Register, Break Point,
> No breakpoint at 0x00007360 Then here are Q&As. Q1. If 0-4 is
> successful, repeat 1-4 a few times to make sure that results are
> consistent. results?? See the error message above. Q2. What are the
> contents of your GEL file?? paste in your next post. /*----------------
> ----------*/ /*
>
EVMDM642.gel
*/ /* Version 1.70
*/
/*--------------------------*/ /* The
StartUp() function is called each time CCS is started. */ /*
Customize this
function to perform desired initialization. */
/*--------------------------*/ StartUp() {
setup_memory_map(); GEL_Reset();
init_emif(); }
/*--------------------------*/ /* Setup
memory map for DM642
EVM.
*/
/*
*/
/*--------------------------*/
setup_memory_map() { GEL_MapOn(); GEL_MapReset();
/* On-chip memory map */
GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal
Memory */
GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL
REGS */
GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL
REGS */
GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL
REGS */
GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL
REGS */
GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL
REGS */
GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL
REGS */
GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL
REGS */
GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND PARAM
*/
GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL
REGS */
GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL
REGS */
GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL
REGS */
GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO
REGS */
GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device Configuration */
GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL
REGS */
GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL
REGS */
GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL
REGS */
GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM
REGS */
GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0
Control */
GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1
Control */
GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2
Control */
GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL
REGS */
GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC
Wrapper */
GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP
REGS */
GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL
REGS */
GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA
REGS */
GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data, EDMA map */
GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data, EDMA map */
GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel A
Data */
GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel B
Data */
GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel A
Data */
GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel B
Data */
GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel A
Data */
GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel B
Data */ /*
Off-chip memory map */ GEL_MapAdd(0x80000000, 0, 0x02000000,
1, 1); /* 32MB
SDRAM EMIF-A, CE0*/ GEL_MapAdd(0x90000000, 0, 0x00080000, 1,
1); /* 4MB
Flash EMIF-A, CE1 */ GEL_MapAdd(0x90080000, 0, 0x00080000, 1,
1); /* 4MB
FPGA EMIF-A, CE1 */
GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /*
EMIF-A, CE2 EXPANSION */ GEL_MapAdd(0xB0000000, 0,
0x10000000, 1, 1); /*
EMIF-A, CE3 EXPANSION */ }
/*--------------------------*/ /*
init_emif()
*/
/*--------------------------*/ init_emif() { > #define
EMIFA_GCTL 0x01800000
> #define EMIFA_CE1 0x01800004
> #define EMIFA_CE0 0x01800008
> #define EMIFA_CE2 0x01800010
> #define EMIFA_CE3 0x01800014
> #define EMIFA_SDRAMCTL 0x01800018
> #define EMIFA_SDRAMTIM 0x0180001c
> #define EMIFA_SDRAMEXT 0x01800020
> #define EMIFA_CE1SECCTL 0x01800044
> #define EMIFA_CE0SECCTL 0x01800048
> #define EMIFA_CE2SECCTL 0x01800050
> #define EMIFA_CE3SECCTL 0x01800054
>
> /* EMIFA */
> *(int *)EMIFA_GCTL = 0x00052078;
> *(int *)EMIFA_CE0 =
0xffffffd3; /* CE0
>
SDRAM
*/ *(int *)
> EMIFA_CE1 = 0x73a28e01; /* CE1 Flash +
>
CPLD
*/ *(int *)EMIFA_CE2 >
0x22a28a22; /* CE2 Daughtercard 32-bit async */ *(int
*)
> EMIFA_CE3 = 0x22a28a42; /* CE3
Daughtercard 32-bit sync
> */ *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM
>
control
*/ *(int *)
> EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing
(refresh)
> */ *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM
extended
> control */ *(int
*)EMIFA_CE0SECCTL= 0x00000002;
> /* CE0 Secondary Control Reg. */ *(int
*)EMIFA_CE1SECCTL> 0x00000002; /* CE1 Secondary Control
Reg. */ *(int *)
> EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control
Reg. */
> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary
Control
> Reg. */ } /*---------------
> -----------*/ /* clear_memory_map()
>
*/ /*--------------------------*/
clear_memory_map() { GEL_MapOff(); }
/*--------------------------*/ /*
FlushCache()
*/
/*--------------------------*/
FlushCache() { /* Invalidate L1I and L1D */
*(int *)0x01840000 (*(int *)0x01840000 | 0x00000300);
/* Clean L2 */ *(int
*)0x01845004
= 0x1; } >
> /*--------------------------*/
> /* OnReset()
>
*/ /*--------------------------*/ OnReset(int
nErrorCode) { init_emif(); } >
> /*--------------------------*/
> /* OnPreFileLoaded()
>
*/ /* This function is called automatically when the 'Load Program'*/ /* Menu item is
selected.
*/
/*--------------------------*/
OnPreFileLoaded() { /* GEL_Reset(); -- Commented out for CCS 2.20
*/
FlushCache(); IER = 0; IFR = 0; init_emif(); }
/*--------------------------*/ /*
OnRestart()
*/ /* This function
is called by CCS when you do Debug->Restart. */ /* The goal is to
put the C6x
into a known good state with */ /* respect to
cache, edma and
interrupts.
*/ /* Failure to do this can cause problems
when you restart and */ /* run your application code multiple
times. This is
different */ /* then OnPreFileLoaded() which will do a GEL_Reset() to get
the*/
/* C6x into a known good
state.
*/
/*--------------------------*/ OnRestart(int
nErrorCode ) { /* Turn off L2 for all EMIFA CE
spaces. App should
* manage these for coherancy in the application.
* GEL_TextOut("Turn off
cache segment\n"); */
*(int *)0x1848200 = 0; /* MAR0 */
*(int
*)0x1848204 = 0; /* MAR1 */ *(int
*)0x1848208 = 0; /* MAR2 */
*(int *)0x184820c = 0; /* MAR3 */
/* Disable EDMA events and
interrupts and clear any * pending events.
* GEL_TextOut("Disable
EDMA event\n");
*/
*(int *)0x01A0FFA8 =
0;
/* CIERH */
*(int *)0x01A0FFB4 =
0; /* EERH */
*(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
*(int *)0x01A0FFE8
= 0; /* CIERL
*/
*(int *)0x01A0FFF4 =
0; /*
EERL */ *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL
*/ /* Disable
other interrupts */ IER = 0;
IFR = 0; }
/*--------------------------*/ /* RESET
MENU
*/
/*--------------------------*/ menuitem
"Resets"; hotmenu Reset_BreakPts_and_EMIF() { GEL_BreakPtReset();
GEL_Reset();
init_emif(); } hotmenu Flush_Cache() { FlushCache(); }
/*--------------------------*/ /* MEMORY MAP
MENU
*/
/*--------------------------*/ menuitem
"Memory Map"; hotmenu SetMemoryMap() { setup_memory_map(); } hotmenu
ClearMemoryMap() { clear_memory_map(); }
/*--------------------------*/ /* BOARD
OPTIONS
MENU
*/
/*--------------------------*/ menuitem
"Board Options"; > #define CPLD_REVISION 0x9008001F
> hotmenu CheckFPGARevision()
> {
> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char *)
> CPLD_REVISION); GEL_TextOut(" Note: Revision only valid if FGPA DONE
> LED is on
> (DS9)\n","Output",1,1,1); }
>
> Q3. What is your target board??
> EVMDM642
> 720MHz
>
> ________________________________
> From: mikedunn
> To: Yi Guo
> Cc: c...
> Sent: Thu, February 17, 2011 3:21:51 AM
> Subject: Re: [c6x] problem with using clock() and printf()
>
>
> Yi Guo,
>
> OK, lets see if we can get a set of consistent symptoms.
> Note that the steps below apply to first and second generation C6000
> devices [like 6201, 6713, 6416] in addition to the DM642. Do not use
> with C64+ devices. The following steps will are not likely to resolve
> your problem, but they will eliminate any doubts WRT extraneous
> interrupts and possible erratic reset behavior. IMO it is always good
> practice to initialize the interrupt vectors when troubleshooting [I
> plug them with breakpoints - if you get an unexpected interrupt, you
> know it right away]. STEP 1: First a minor change to the .cmd file.
> add the 'VECS' and '.vectors' lines as shown below:
--begin-- MEMORY {
> VECS: org = 000h, len = 400h IRAM: org =
400h, len = 0FC00h
> }
> SECTIONS
> {
> .vectors :> VECS
> ------end of changes---
> STEP 2:
> Then add the code below to a file called 'vectors.asm'.
> Begin 'vectors.asm'---------
> ;
> ; Copyright 2003 by Texas Instruments Incorporated.
> ; All rights reserved. Property of Texas Instruments Incorporated.
> ; Restricted rights to use, duplicate or disclose this code are
> ; granted through contract.
> ;
> ;
> ; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
> ; hacked by mikedunn
> ;
>
> unused .macro id
>
> .global unused:id:
> unused:id:
> nop
> nop
> .word 0x10000000
;breakpoint opcode
> nop
> nop
> nop
> nop
> nop
>
> .endm
>
> .sect ".vectors"
>
> .ref
_c_int00 ; C
entry point
> .def RESET
; reset vector
> .align
32*8*4 ; must be aligned
on
> 256 word boundary
>
>
RESET:
; reset vector
> mvkl
_c_int00,b0 ; load destination
> function address to b0 mvkh
_c_int00,b0
> b
b0
; start branch to
> destination function
>
nop
>
nop
>
nop
nop
> nop
>
> ;
> ; plug unused interrupts with
breakpoints to
> ; catch stray interrupts
> ;
> unused 1
> unused 2
> unused 3
> unused 4
> unused 5
> unused 6
> unused 7
> unused 8
> unused 9
> unused 10
> unused 11
> unused 12
> unused 13
> unused 14
> unused 15
>
> End 'vectors.asm'---------
> STEP 3:
> The above changes will do 2 things - reserve the 1k boot area [not so
> important in this case] and plug all of the default interrupt vectors
> [except for reset] with breakpoints. There will be a branch to the C
> program entry point [c_int00] at the reset vector. Change your CCS
> build options by adding 'RESET' to the text box at:
'Project-
> >BuildOptions->Linker->CodeEntryPoint'
>
> note: You will get a warning when you rebuild.
> >> warning: entry point other than _c_int00 specified
> [I have no idea why the warning - the reset vector entry point is the
> correct entry point for an embedded application]
>
> When you load the program, the 'green arrow' in the disassembly
window
> should point to the address 0.
>
> Now we are ready to test. Do not get caught up with 'trying to get it
> to run'. Your goal when you have a problem is to establish a
> repeatable 'first failure'.
> 0. Make sure that your project is built with the debug option - no
> optimization [thanx for the reminder Richard - bad assumption on my part]
> 1. Power up the target and connect CCS.
> 2. Load the program - Do not do a CPU reset.
> 3. Do a debug->Go main.
> 4. Run the target.
> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that
> results are consistent. results?? Q2. What are the contents of your
> GEL file?? paste in your next post. Q3. What is your target board??
> Q4. What is the CPU clock rate??
>
> mikedunn
>
> On 2/15/2011 7:30 PM, Yi Guo wrote:
> Mikedunn and Jeff,
> >
> >I'm sorry I snipped the message. Thank you for helping me.
> >Step 1:
> >1, I compile the program.
> >2, reset the CPU by DEBUG-->RESET CPU.
> >3, load the program.
> >At this time, everything looks good. 4. Run. CCS issue an error: Error:
Error
> >0x0000000C/-2044 Error during: Register, Break Point, No breakpoint at
> >0x00006F00. At this moment I can't halt the program.
> >Step 2:
> >I repet 2 and 3 of Step 1, at this time, CCS gives the following message.
> >Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
> >breakpoint at 0x00006F00
> >
> >Trouble Removing Breakpoint with the Action "Terminate Program Execution" at
> >0x6f00: Error 0x00000008/-1076 Error during: Break Point, Cannot
set/verify
> >breakpoint at 0x00006F00
> >
> >
> >There was a suprise, I don't whether this is solution to the problem. I
changed
> >the stack size from 400h to 500 h, there were no errors, and it halted
at a s/w
> >breakpoint if I run the program. Some information from disassembly window is
> >shown as bellow.
> >00006F00 abort,
C$$EXIT:
> >00006F00
00000000
NOP
> >00006F04
0001A120
BNOP.S1 0x6F04 (PC+4 = 0x00006f04),5
> >00006F08
00000000
NOP
> >00006F0C
00000000
NOP
> >00006F10
00000000
NOP
> >00006F14
00000000
NOP
> >00006F18
00000000
NOP
> >00006F1C
00000000 NOP
> >
> >Here are the answers to your questions.
> >
> >Q1. What is your emulator's manufacturer name and model number??
> >> XDS 510, USB2.0 TI dsp emulator.
> >
> >Do the following with CCS up:
> >1. reset the DSP
> >2. load the program. I assume that you will get a failure at 0x00006F60.
> >3. open the disassembly window if it is not open.
> >4. goto address 0x00006000 and highlight from there to 0x000070000. right
click
> >the highlighted block, select copy. then paste it into your reply.
> >>00006F00 abort,
C$$EXIT:
> >00006F00
00000000
NOP
> >00006F04
0001A120
BNOP.S1 0x6F04 (PC+4 = 0x00006f04),5
> >00006F08
00000000
NOP
> >00006F0C
00000000
NOP
> >00006F10
00000000
NOP
> >00006F14
00000000
NOP
> >00006F18
00000000
NOP
> >00006F1C
00000000
NOP
> >00006F20 clock:
> >00006F20
0FFDD010
B.S1 HOSTclock (PC-4480 =
0x00005da0)
> >00006F24
00008000
NOP 5
> >00006F28
00000000
NOP
> >00006F2C
00000000
NOP
> >00006F30
00000000
NOP
> >00006F34
00000000
NOP
> >00006F38
00000000
NOP
> >00006F3C
00000000
NOP
> >00006F40 remove:
> >00006F40
0FFF8810
B.S1 unlink (PC-960 =
0x00006b80)
> >00006F44
00008000
NOP 5
> >00006F48
00000000
NOP
> >00006F4C
00000000
NOP
> >00006F50
00000000
NOP
> >00006F54
00000000
NOP
> >00006F58
00000000
NOP
> >00006F5C
00000000
NOP
> >00006F60 etext,
__etext, _stack:
> >00006F60
00000001
NOP
> >00006F64 00000000 ||
NOP
> >00006F68 30303030 [!B0]
MPY2.M1X A1,B12,A1:A0
> >00006F6C 30303030 [!B0]
MPY2.M1X A1,B12,A1:A0
> >00006F70
00000030
MPY2.M1 A0,A0,A1:A0
> >00006F74
00000000
NOP
> >00006F78
00000000
NOP
> >00006F7C
00000000
NOP
> >00006F80 222834E6 [ B0]
LDW.D2T2 *B10--[1],B4
> >00006F84
00004000
NOP 3
> >00006F88
022808F0
OR.D1 0,A10,A4
> >00006F8C
00100362
B.S2 B4
> >00006F90
01858162
ADDKPC.S2 0x6F94 (PC+20 = 0x00006f94),B3,4
> >00006F94
002C29C0
SUB.D1 A11,0x1,A0
> >00006F98 C0000110 [ A0]
B.S1 0x6F88 (PC+8 =
0x00006f88)
> >00006F9C
05AC29C1
SUB.D1 A11,0x1,A11
> >00006FA0 C22834E6 || [ A0] LDW.D2T2
*B10--[1],B4
> >00006FA4 D205B26E [!A0]
LDW.D2T2 *+B14[1458],B4
> >00006FA8
00004000
NOP 3
> >00006FAC
022808F0
OR.D1 0,A10,A4
> >00006FB0
00002000
NOP 2
> >00006FB4
021042E6
LDW.D2T2 *+B4[2],B4
> >00006FB8
00006000
NOP 4
> >00006FBC
00100362
B.S2 B4
> >00006FC0
02878E6E
LDW.D2T2 *+B14[1934],B5
> >00006FC4
00002000
NOP 2
> >00006FC8
020ECC2A
MVK.S2 0x1d98,B4
> >00006FCC
02388842
ADD.D2 DP,B4,B4
> >00006FD0
021488C2
SUB.D2 B5,B4,B4
> >00006FD4
02104DA2
SHR.S2 B4,0x2,B4
> >00006FD8
00100ADA
CMPLT.L2 0,B4,B0
> >00006FDC 30000D90 [!B0]
B.S1 0x702C (PC+108 =
0x0000702c)
> >00006FE0
053C94F6
STW.D2T2 B10,*SP--[4]
> >00006FE4
053C23C4
STDW.D2T1 A11:A10,*+SP[1]
> >00006FE8
051006A1
OR.S1 0,A4,A10
> >00006FEC 0517805B ||
SUB.L2 B5,4,B10
> >00006FF0 068C06A3 ||
OR.S2 0,B3,B13
> >00006FF4 06BC22F7 ||
STW.D2T2 B13,*+SP[1]
> >00006FF8 059018F0 ||
OR.D1X 0,B4,A11
> >00006FFC 3205B26E [!B0]
LDW.D2T2 *+B14[1458],B4
> >00007000
00000000
NOP
> >
> >5. open a memory window at 0x00006F60.
> >6. open a second memory window at 0x00046F60. I'm not sure if this will
> >work-some c6x devices will 'mirror' the memory contents of internal
memory. If
> >this works, I expect all locations to be the same EXCEPT for 0x00006F60 &
> >0x00046F60. If this is true, copy the contents of 0x00046F60 and paste in
your
> >reply.
> >>
> >0x00006F00 abort, C$$EXIT
> >0x00006F00 0x00000000 0x0001A120
> >0x00006F08 0x00000000 0x00000000
> >0x00006F10 0x00000000 0x00000000
> >0x00006F18 0x00000000 0x00000000
> >0x00006F20 clock
> >0x00006F20 0x0FFDD010 0x00008000
> >0x00006F28 0x00000000 0x00000000
> >
> >
> >0x00046F00 -------- --------
> >0x00046F08 -------- --------
> >0x00046F10 -------- --------
> >0x00046F18 -------- --------
> >0x00046F20 -------- --------
> >0x00046F28 -------- --------
> >0x00046F30 -------- --------
> >
> >
> >
> >
> >
> >
> >
> ________________________________
> From: mikedunn
> >To: u...@yahoo.com
> >Cc: c...
> >Sent: Wed, February 16, 2011 7:35:58 AM
> >Subject: Re: [c6x] problem with using clock() and printf()
> >
> >unicogse and OTHERS,
> >
> >Do NOT snip messages if you want assistance. It is important to maintain the
> >history. I deal in several problems a day and I cannot remember details about
> >each one - also, there are others who may have missed the original message.
Some
> >of us are very busy professionals who donate time to HELP EVERYONE LEARN and
we
> >do not have time to go back and research the history. I took the time to
write
> >this so that it can be a learning experience for you and others.
> >
> >Please see my comments inline below.
> >
> >mikedunn
> >
> >On 2/14/2011 12:44 AM, mikedunn wrote:
> >unicogse,
> >>
> >>On 2/13/2011 8:41 PM, u...@yahoo.com wrote:
> >>
> >>>Hi,all,
> >>>when use the following .cmd and .c files, and load the generated .out file,
I
> >>>encountered an error:
> >>>"Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
> >>>breakpoint at 0x00006F60
> >>>Trouble Removing Breakpoint with the Action "Terminate Program Execution"
at
> >>>0x6f60: Error 0x00000008/-1076 Error during: Break Point, Cannot set/verify
> >>>breakpoint at 0x00006F60"
> >>>
> A few possibilities...
> Your target is broken, CCS is not configured correctly, or your
> project is not set up correctly. The following questions should help
> sort it out. Q1. Have you compiled, loaded, and run a program
> correctly using this target and emulator??
> >yes
>
> Q2. Does your project include rts6400.lib??
> Check CCS 'Option->Customize->Program/Project/CIO' tab.
> >yes, I did.
>
> Q3. Is 'Do not Set CIO Breakpoint at Load' checked?? [it should NOT
be]
> >No.
>
> Q4. Is 'Do Not Set End of Program Breakpoint at Load' checked?? [it
> should NOT be]
> >No.
>
> Q5. Is 'Disable All Breakpoints When Loading New Programs' checked??
> [it should NOT be]
> >No.
>
> Open a memory window in CCS at location 0x00006F60 while connected to
> the target.
> Change the contents to 0xAAAAAAAA and refresh the window.
> Q6. Does the window show 0xAAAAAAAA??
> >yes
>
> Change the contents to 0x55555555 and refresh the window.
> Q7. Does the window show 0x55555555??
> >yes
>
> This tells me that you hardware and emulator appear to be working.
> Your original error message indicates that there was problems setting
> or clearing a breakpoint. The simple exercise of reading and writing
> memory proved that it can be done [setting a sw breakpoint [BP]
> involves reading a memory location, saving the value, and writing a BP
> opcode into the memory location. The issue is compounded by CCS
> "helping you" when memory is displayed. If a location is known to have
> a BP, CCS shows you the original location contents instead of the
> actual location contents. My gut feeling is that there is a basic
> mistake that is being missed somewhere. Q1. What is your emulator's
> manufacturer name and model number?? Do the following with CCS up:
> 1. reset the DSP
> 2. load the program. I assume that you will get a failure at 0x00006F60.
> 3. open the disassembly window if it is not open.
> 4. goto address 0x00006000 and highlight from there to 0x000070000.
> right click the highlighted block, select copy. then paste it into
> your reply.
> 5. open a memory window at 0x00006F60.
> 6. open a second memory window at 0x00046F60. I'm not sure if this
> will work-some c6x devices will 'mirror' the memory contents of
> internal memory. If this works, I expect all locations to be the same
> EXCEPT for 0x00006F60 & 0x00046F60. If this is true, copy the contents
> of 0x00046F60 and paste in your reply.
>
> mikedunn
>
> >FYI-
> >The timing info will be misleading on an embedded system.
> >stdio on TI's embedded devices works something like this for each stdio
function
> >[printf, time, etc]:
> >1. A hidden BP is set using special label when the program is loaded.
> >2. When the program is run, it halts at the BP.
> >3. CCS polls the target for run or halt. If the program is halted, CCS checks
> >the label in the symbol table.
> >4. If it is a stdio BP, CCS will read memory - I think it is the first add
after
> >the BP. The add contains an opcode that indicates the course of action.
> >5 Once CCS 'does its duty' according to the opcode, a run command
is issued to
> >the target.
> >All of this makes stdio very s-l-o-w.
> >
> >mikedunn
> >
> >
> >
> >
> >>If the program runs, it can't go to the end. This problem has confused
me for
> >>days. Any hints are welcome. Thank you in advance.
> >>
> >>Evironment:
> >>DM642, CCS3.3
> >>
> >>CODE:
> >>main.cmd
> >>MEMORY
> >>{
> >>IRAM: org = 0h, len = 10000h
> >>}
> >>
> >>SECTIONS
> >>{
> >>.data :> IRAM
> >>.text :> IRAM
> >>.switch :> IRAM
> >>.stack :> IRAM
> >>.bss :> IRAM
> >>.cinit :> IRAM
> >>.far :> IRAM
> >>.cio :> IRAM
> >>.const :> IRAM
> >>.sysmem :> IRAM
> >>.tables :> IRAM
> >>}
> >>
> >>main.c
> >>
> >>#include
> >>#include
> >>
> >>void main()
> >>{
> >>int j, a = 0;
> >>clock_t start, finish;
> >>double duration;
> >>start = clock();
> >>for (j = 0; j < 3; j++) {
> >>a += 1;
> >>}
> >>finish = clock();
> >>duration = (double)(finish -start) / CLOCKS_PER_SEC;
> >>printf("%f\n", duration);
> >>}
> >> Q4. What is the CPU clock rate?? ------- End of Original Message -------
_____________________________________
Reply by mikedunn●February 17, 20112011-02-17
Yi Guo,
On 2/16/2011 7:05 PM, Yi Guo wrote: > Mikedunn,
>
> Thank you for help.
>
> I didn't find any optimization options were selected:
>
> Build option-->compiler-->opt level-->none
>
> Build option-->compiler-->program level opt-->none
>
> I followed the steps you provided to do some test for some times, I
> always received an error message from CCS:
>
> Error: Error 0x0000000C/-2044 Error during: Register, Break Point, No
> breakpoint at 0x00007360
>
You need to give a little help.
Q1. What label is at 0x00007360??
Q2. When did the error occur?? During program load, go main, or run??
Try unloading the GEL file.
Q3. Do you get the same results??
If the error is at the clock() BP, change your code to eliminate clock()
calls and replace start and finish with hardcoded values like 1 and 8.
Try the 1-4.
Q3. Do you still get an error??
Q4. If yes, what is the error??
Q5. If it is a BP error, what is at that address??
mikedunn > Then here are Q&As.
>
> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that
> results are consistent. results??
>
> See the error message above.
>
> Q2. What are the contents of your GEL file?? paste in your next post.
> /*--------------------------*/
> /* EVMDM642.gel */
> /* Version 1.70 */
>
> /*--------------------------*/
> /* The StartUp() function is called each time CCS is started. */
> /* Customize this function to perform desired initialization. */
> /*--------------------------*/
>
> StartUp()
> {
> setup_memory_map();
> GEL_Reset();
> init_emif();
> }
>
> /*--------------------------*/
> /* Setup memory map for DM642 EVM. */
> /* */
> /*--------------------------*/
> setup_memory_map()
> {
>
> GEL_MapOn();
> GEL_MapReset();
>
> /* On-chip memory map */
> GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal
> Memory */
> GEL_MapAdd(0x01800000, 0, 0x00000058, 1, 1); /* EMIFA CTL
> REGS */
> GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL
> REGS */
> GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL
> REGS */
> GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL
> REGS */
> GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL
> REGS */
> GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL
> REGS */
> GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL
> REGS */
> GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND
> PARAM */
> GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL
> REGS */
> GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL
> REGS */
> GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL
> REGS */
> GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO
> REGS */
> GEL_MapAdd(0x01B3F000, 0, 0x00000020, 1, 1); /* Device
> Configuration */
> GEL_MapAdd(0x01B40000, 0, 0x0000003C, 1, 1); /* I2C CTL
> REGS */
> GEL_MapAdd(0x01B4C000, 0, 0x000002A0, 1, 1); /* McASP0 CTL
> REGS */
> GEL_MapAdd(0x01C00000, 0, 0x00000028, 1, 1); /* PCI CTL
> REGS */
> GEL_MapAdd(0x01C20000, 0, 0x0000000C, 1, 1); /* PCI EEPROM
> REGS */
> GEL_MapAdd(0x01C40000, 0, 0x00000270, 1, 1); /* VP0
> Control */
> GEL_MapAdd(0x01C44000, 0, 0x00000270, 1, 1); /* VP1
> Control */
> GEL_MapAdd(0x01C48000, 0, 0x00000270, 1, 1); /* VP2
> Control */
> GEL_MapAdd(0x01C80000, 0, 0x00000680, 1, 1); /* EMAC CTL
> REGS */
> GEL_MapAdd(0x01C81000, 0, 0x00002000, 1, 1); /* EMAC
> Wrapper */
> GEL_MapAdd(0x01C83000, 0, 0x0000000C, 1, 1); /* EWRAP
> REGS */
> GEL_MapAdd(0x01C83800, 0, 0x00000090, 1, 1); /* MDIO CTL
> REGS */
> GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA
> REGS */
> GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data, EDMA
> map */
> GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data, EDMA
> map */
> GEL_MapAdd(0x74000000, 0, 0x02000000, 1, 1); /* VP0 Channel A
> Data */
> GEL_MapAdd(0x76000000, 0, 0x02000000, 1, 1); /* VP0 Channel B
> Data */
> GEL_MapAdd(0x78000000, 0, 0x02000000, 1, 1); /* VP1 Channel A
> Data */
> GEL_MapAdd(0x7A000000, 0, 0x02000000, 1, 1); /* VP1 Channel B
> Data */
> GEL_MapAdd(0x7C000000, 0, 0x02000000, 1, 1); /* VP2 Channel A
> Data */
> GEL_MapAdd(0x7E000000, 0, 0x02000000, 1, 1); /* VP2 Channel B
> Data */
>
> /* Off-chip memory map */
> GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM EMIF-A,
> CE0*/
> GEL_MapAdd(0x90000000, 0, 0x00080000, 1, 1); /* 4MB Flash EMIF-A,
> CE1 */
> GEL_MapAdd(0x90080000, 0, 0x00080000, 1, 1); /* 4MB FPGA EMIF-A,
> CE1 */
> GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE2
> EXPANSION */
> GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3
> EXPANSION */
> }
>
> /*--------------------------*/
> /* init_emif() */
> /*--------------------------*/
> init_emif()
> {
>
> #define EMIFA_GCTL 0x01800000
> #define EMIFA_CE1 0x01800004
> #define EMIFA_CE0 0x01800008
> #define EMIFA_CE2 0x01800010
> #define EMIFA_CE3 0x01800014
> #define EMIFA_SDRAMCTL 0x01800018
> #define EMIFA_SDRAMTIM 0x0180001c
> #define EMIFA_SDRAMEXT 0x01800020
> #define EMIFA_CE1SECCTL 0x01800044
> #define EMIFA_CE0SECCTL 0x01800048
> #define EMIFA_CE2SECCTL 0x01800050
> #define EMIFA_CE3SECCTL 0x01800054
>
> /* EMIFA */
> *(int *)EMIFA_GCTL = 0x00052078;
> *(int *)EMIFA_CE0 = 0xffffffd3; /* CE0
> SDRAM */
> *(int *)EMIFA_CE1 = 0x73a28e01; /* CE1 Flash +
> CPLD */
> *(int *)EMIFA_CE2 = 0x22a28a22; /* CE2 Daughtercard 32-bit
> async */
> *(int *)EMIFA_CE3 = 0x22a28a42; /* CE3 Daughtercard 32-bit
> sync */
> *(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM
> control */
> *(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing
> (refresh) */
> *(int *)EMIFA_SDRAMEXT = 0x001faf4d; /* SDRAM extended
> control */
> *(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control
> Reg. */
> *(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control
> Reg. */
> *(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control
> Reg. */
> *(int *)EMIFA_CE3SECCTL= 0x00000073; /* CE3 Secondary Control
> Reg. */
> }
>
> /*--------------------------*/
> /* clear_memory_map() */
> /*--------------------------*/
> clear_memory_map()
> {
> GEL_MapOff();
> }
>
> /*--------------------------*/
> /* FlushCache() */
> /*--------------------------*/
> FlushCache()
> {
> /* Invalidate L1I and L1D */
> *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
>
> /* Clean L2 */
> *(int *)0x01845004 = 0x1;
> }
> /*--------------------------*/
> /* OnReset() */
> /*--------------------------*/
> OnReset(int nErrorCode)
> {
> init_emif();
> }
> /*--------------------------*/
> /* OnPreFileLoaded() */
> /* This function is called automatically when the 'Load
Program'*/
> /* Menu item is selected. */
> /*--------------------------*/
> OnPreFileLoaded()
> {
> /* GEL_Reset(); -- Commented out for CCS 2.20 */
> FlushCache();
> IER = 0;
> IFR = 0;
> init_emif();
> }
>
> /*--------------------------*/
> /* OnRestart() */
> /* This function is called by CCS when you do Debug->Restart. */
> /* The goal is to put the C6x into a known good state with */
> /* respect to cache, edma and interrupts. */
> /* Failure to do this can cause problems when you restart and */
> /* run your application code multiple times. This is different */
> /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/
> /* C6x into a known good state. */
> /*--------------------------*/
> OnRestart(int nErrorCode )
> {
> /* Turn off L2 for all EMIFA CE spaces. App should
> * manage these for coherancy in the application.
> * GEL_TextOut("Turn off cache segment\n");
> */
> *(int *)0x1848200 = 0; /* MAR0 */
> *(int *)0x1848204 = 0; /* MAR1 */
> *(int *)0x1848208 = 0; /* MAR2 */
> *(int *)0x184820c = 0; /* MAR3 */
>
> /* Disable EDMA events and interrupts and clear any
> * pending events.
> * GEL_TextOut("Disable EDMA event\n");
> */
> *(int *)0x01A0FFA8 = 0; /* CIERH */
> *(int *)0x01A0FFB4 = 0; /* EERH */
> *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */
>
> *(int *)0x01A0FFE8 = 0; /* CIERL */
> *(int *)0x01A0FFF4 = 0; /* EERL */
> *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */
>
> /* Disable other interrupts */
> IER = 0;
> IFR = 0;
> }
>
> /*--------------------------*/
> /* RESET MENU */
> /*--------------------------*/
> menuitem "Resets";
>
> hotmenu Reset_BreakPts_and_EMIF()
> {
> GEL_BreakPtReset();
> GEL_Reset();
> init_emif();
> }
>
> hotmenu Flush_Cache()
> {
> FlushCache();
> }
>
> /*--------------------------*/
> /* MEMORY MAP MENU */
> /*--------------------------*/
> menuitem "Memory Map";
>
> hotmenu SetMemoryMap()
> {
> setup_memory_map();
> }
>
> hotmenu ClearMemoryMap()
> {
> clear_memory_map();
> }
>
> /*--------------------------*/
> /* BOARD OPTIONS MENU */
> /*--------------------------*/
> menuitem "Board Options";
>
> #define CPLD_REVISION 0x9008001F
>
> hotmenu CheckFPGARevision()
> {
> GEL_TextOut(" FPGA Revision %d\n","Output",1,1,1, *(char
> *)CPLD_REVISION);
> GEL_TextOut(" Note: Revision only valid if FGPA DONE LED is on
> (DS9)\n","Output",1,1,1);
> }
>
> Q3. What is your target board??
>
> EVMDM642
> Q4. What is the CPU clock rate??
> 720MHz
>
>
> *From:* mikedunn
> *To:* Yi Guo
> *Cc:* c...
> *Sent:* Thu, February 17, 2011 3:21:51 AM
> *Subject:* Re: [c6x] problem with using clock() and printf()
>
> Yi Guo,
>
> OK, lets see if we can get a set of consistent symptoms.
> Note that the steps below apply to first and second generation C6000
> devices [like 6201, 6713, 6416] in addition to the DM642. Do not use
> with C64+ devices.
> The following steps will are not likely to resolve your problem, but
> they will eliminate any doubts WRT extraneous interrupts and possible
> erratic reset behavior. IMO it is always good practice to initialize
> the interrupt vectors when troubleshooting [I plug them with
> breakpoints - if you get an unexpected interrupt, you know it right away].
> STEP 1:
> First a minor change to the .cmd file. add the 'VECS' and
'.vectors'
> lines as shown below:
> --begin--
> MEMORY
> {
> VECS: org = 000h, len = 400h
> IRAM: org = 400h, len = 0FC00h
> }
> SECTIONS
> {
> .vectors :> VECS
> ------end of changes---
> STEP 2:
> Then add the code below to a file called 'vectors.asm'.
> Begin 'vectors.asm'---------
> ;
> ; Copyright 2003 by Texas Instruments Incorporated.
> ; All rights reserved. Property of Texas Instruments Incorporated.
> ; Restricted rights to use, duplicate or disclose this code are
> ; granted through contract.
> ;
> ;
> ; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
> ; hacked by mikedunn
> ;
>
> unused .macro id
>
> .global unused:id:
> unused:id:
> nop
> nop
> .word 0x10000000 ;breakpoint opcode
> nop
> nop
> nop
> nop
> nop
>
> .endm
>
> .sect ".vectors"
>
> .ref _c_int00 ; C entry point
> .def RESET ; reset vector
> .align 32*8*4 ; must be aligned on 256 word boundary
>
> RESET: ; reset vector
> mvkl _c_int00,b0 ; load destination function address to b0
> mvkh _c_int00,b0
> b b0 ; start branch to destination function
> nop
> nop
> nop
> nop
> nop
>
> ;
> ; plug unused interrupts with breakpoints to
> ; catch stray interrupts
> ;
> unused 1
> unused 2
> unused 3
> unused 4
> unused 5
> unused 6
> unused 7
> unused 8
> unused 9
> unused 10
> unused 11
> unused 12
> unused 13
> unused 14
> unused 15
>
> End 'vectors.asm'---------
> STEP 3:
> The above changes will do 2 things - reserve the 1k boot area [not so
> important in this case] and plug all of the default interrupt vectors
> [except for reset] with breakpoints. There will be a branch to the C
> program entry point [c_int00] at the reset vector. Change your CCS
> build options by adding 'RESET' to the text box at:
> 'Project->BuildOptions->Linker->CodeEntryPoint'
>
> note: You will get a warning when you rebuild.
> >> warning: entry point other than _c_int00 specified
> [I have no idea why the warning - the reset vector entry point is the
> correct entry point for an embedded application]
>
> When you load the program, the 'green arrow' in the disassembly
window
> should point to the address 0.
>
> Now we are ready to test. Do not get caught up with 'trying to get it
> to run'. Your goal when you have a problem is to establish a
> repeatable 'first failure'.
> 0. Make sure that your project is built with the debug option - no
> optimization [thanx for the reminder Richard - bad assumption on my part]
> 1. Power up the target and connect CCS.
> 2. Load the program - Do not do a CPU reset.
> 3. Do a debug->Go main.
> 4. Run the target.
> Q1. If 0-4 is successful, repeat 1-4 a few times to make sure that
> results are consistent. results??
> Q2. What are the contents of your GEL file?? paste in your next post.
> Q3. What is your target board??
> Q4. What is the CPU clock rate??
>
> mikedunn
>
> On 2/15/2011 7:30 PM, Yi Guo wrote:
>
>> Mikedunn and Jeff,
>> I'm sorry I snipped the message. Thank you for helping me.
>> Step 1:
>> 1, I compile the program.
>> 2, reset the CPU by DEBUG-->RESET CPU.
>> 3, load the program.
>> At this time, everything looks good. 4. Run. CCS issue an error:
>> Error: Error 0x0000000C/-2044 Error during: Register, Break Point,
>> No breakpoint at 0x00006F00. At this moment I can't halt the program.
>> Step 2:
>> I repet 2 and 3 of Step 1, at this time, CCS gives the following message.
>> Error: Error 0x0000000C/-2044 Error during: Register, Break Point,
>> No breakpoint at 0x00006F00
>> Trouble Removing Breakpoint with the Action "Terminate Program
>> Execution" at 0x6f00: Error 0x00000008/-1076 Error during: Break
>> Point, Cannot set/verify breakpoint at 0x00006F00
>> There was a suprise, I don't whether this is solution to the problem.
>> I changed the stack size from 400h to 500 h, there were no errors,
>> and it halted at a s/w breakpoint if I run the program. Some
>> information from disassembly window is shown as bellow.
>> 00006F00 abort, C$$EXIT:
>> 00006F00 00000000 NOP
>> 00006F04 0001A120 BNOP.S1 0x6F04 (PC+4 = 0x00006f04),5
>> 00006F08 00000000 NOP
>> 00006F0C 00000000 NOP
>> 00006F10 00000000 NOP
>> 00006F14 00000000 NOP
>> 00006F18 00000000 NOP
>> 00006F1C 00000000 NOP
>> Here are the answers to your questions.
>> Q1. What is your emulator's manufacturer name and model number??
>> > XDS 510, USB2.0 TI dsp emulator.
>> Do the following with CCS up:
>> 1. reset the DSP
>> 2. load the program. I assume that you will get a failure at 0x00006F60.
>> 3. open the disassembly window if it is not open.
>> 4. goto address 0x00006000 and highlight from there to 0x000070000.
>> right click the highlighted block, select copy. then paste it into
>> your reply.
>> >00006F00 abort, C$$EXIT:
>> 00006F00 00000000 NOP
>> 00006F04 0001A120 BNOP.S1 0x6F04 (PC+4 = 0x00006f04),5
>> 00006F08 00000000 NOP
>> 00006F0C 00000000 NOP
>> 00006F10 00000000 NOP
>> 00006F14 00000000 NOP
>> 00006F18 00000000 NOP
>> 00006F1C 00000000 NOP
>> 00006F20 clock:
>> 00006F20 0FFDD010 B.S1 HOSTclock (PC-4480 >>
0x00005da0)
>> 00006F24 00008000 NOP 5
>> 00006F28 00000000 NOP
>> 00006F2C 00000000 NOP
>> 00006F30 00000000 NOP
>> 00006F34 00000000 NOP
>> 00006F38 00000000 NOP
>> 00006F3C 00000000 NOP
>> 00006F40 remove:
>> 00006F40 0FFF8810 B.S1 unlink (PC-960 = 0x00006b80)
>> 00006F44 00008000 NOP 5
>> 00006F48 00000000 NOP
>> 00006F4C 00000000 NOP
>> 00006F50 00000000 NOP
>> 00006F54 00000000 NOP
>> 00006F58 00000000 NOP
>> 00006F5C 00000000 NOP
>> 00006F60 etext, __etext, _stack:
>> 00006F60 00000001 NOP
>> 00006F64 00000000 || NOP
>> 00006F68 30303030 [!B0] MPY2.M1X A1,B12,A1:A0
>> 00006F6C 30303030 [!B0] MPY2.M1X A1,B12,A1:A0
>> 00006F70 00000030 MPY2.M1 A0,A0,A1:A0
>> 00006F74 00000000 NOP
>> 00006F78 00000000 NOP
>> 00006F7C 00000000 NOP
>> 00006F80 222834E6 [ B0] LDW.D2T2 *B10--[1],B4
>> 00006F84 00004000 NOP 3
>> 00006F88 022808F0 OR.D1 0,A10,A4
>> 00006F8C 00100362 B.S2 B4
>> 00006F90 01858162 ADDKPC.S2 0x6F94 (PC+20 >>
0x00006f94),B3,4
>> 00006F94 002C29C0 SUB.D1 A11,0x1,A0
>> 00006F98 C0000110 [ A0] B.S1 0x6F88 (PC+8 = 0x00006f88)
>> 00006F9C 05AC29C1 SUB.D1 A11,0x1,A11
>> 00006FA0 C22834E6 || [ A0] LDW.D2T2 *B10--[1],B4
>> 00006FA4 D205B26E [!A0] LDW.D2T2 *+B14[1458],B4
>> 00006FA8 00004000 NOP 3
>> 00006FAC 022808F0 OR.D1 0,A10,A4
>> 00006FB0 00002000 NOP 2
>> 00006FB4 021042E6 LDW.D2T2 *+B4[2],B4
>> 00006FB8 00006000 NOP 4
>> 00006FBC 00100362 B.S2 B4
>> 00006FC0 02878E6E LDW.D2T2 *+B14[1934],B5
>> 00006FC4 00002000 NOP 2
>> 00006FC8 020ECC2A MVK.S2 0x1d98,B4
>> 00006FCC 02388842 ADD.D2 DP,B4,B4
>> 00006FD0 021488C2 SUB.D2 B5,B4,B4
>> 00006FD4 02104DA2 SHR.S2 B4,0x2,B4
>> 00006FD8 00100ADA CMPLT.L2 0,B4,B0
>> 00006FDC 30000D90 [!B0] B.S1 0x702C (PC+108 = 0x0000702c)
>> 00006FE0 053C94F6 STW.D2T2 B10,*SP--[4]
>> 00006FE4 053C23C4 STDW.D2T1 A11:A10,*+SP[1]
>> 00006FE8 051006A1 OR.S1 0,A4,A10
>> 00006FEC 0517805B || SUB.L2 B5,4,B10
>> 00006FF0 068C06A3 || OR.S2 0,B3,B13
>> 00006FF4 06BC22F7 || STW.D2T2 B13,*+SP[1]
>> 00006FF8 059018F0 || OR.D1X 0,B4,A11
>> 00006FFC 3205B26E [!B0] LDW.D2T2 *+B14[1458],B4
>> 00007000 00000000 NOP
>>
>> 5. open a memory window at 0x00006F60.
>> 6. open a second memory window at 0x00046F60. I'm not sure if this
>> will work-some c6x devices will 'mirror' the memory contents of
>> internal memory. If this works, I expect all locations to be the same
>> EXCEPT for 0x00006F60 & 0x00046F60. If this is true, copy the
>> contents of 0x00046F60 and paste in your reply.
>> >
>> 0x00006F00 abort, C$$EXIT
>> 0x00006F00 0x00000000 0x0001A120
>> 0x00006F08 0x00000000 0x00000000
>> 0x00006F10 0x00000000 0x00000000
>> 0x00006F18 0x00000000 0x00000000
>> 0x00006F20 clock
>> 0x00006F20 0x0FFDD010 0x00008000
>> 0x00006F28 0x00000000 0x00000000
>> 0x00046F00 -------- --------
>> 0x00046F08 -------- --------
>> 0x00046F10 -------- --------
>> 0x00046F18 -------- --------
>> 0x00046F20 -------- --------
>> 0x00046F28 -------- --------
>> 0x00046F30 -------- --------
>>
>> *From:* mikedunn
>> *To:* u...@yahoo.com
>> *Cc:* c...
>> *Sent:* Wed, February 16, 2011 7:35:58 AM
>> *Subject:* Re: [c6x] problem with using clock() and printf()
>>
>> unicogse and OTHERS,
>>
>> Do NOT snip messages if you want assistance. It is important to
>> maintain the history. I deal in several problems a day and I cannot
>> remember details about each one - also, there are others who may have
>> missed the original message. Some of us are very busy professionals
>> who donate time to HELP EVERYONE LEARN and we do not have time to go
>> back and research the history. I took the time to write this so that
>> it can be a learning experience for you and others.
>>
>> Please see my comments inline below.
>>
>> mikedunn
>>
>> On 2/14/2011 12:44 AM, mikedunn wrote:
>>> unicogse,
>>>
>>> On 2/13/2011 8:41 PM, u...@yahoo.com wrote:
>>>>
>>>> Hi,all,
>>>> when use the following .cmd and .c files, and load the generated
>>>> .out file, I encountered an error:
>>>> "Error: Error 0x0000000C/-2044 Error during: Register, Break Point,
>>>> No breakpoint at 0x00006F60
>>>> Trouble Removing Breakpoint with the Action "Terminate Program
>>>> Execution" at 0x6f60: Error 0x00000008/-1076 Error during: Break
>>>> Point, Cannot set/verify breakpoint at 0x00006F60"
>>>>
>
> A few possibilities...
> Your target is broken, CCS is not configured correctly, or your
> project is not set up correctly. The following questions should help
> sort it out.
> Q1. Have you compiled, loaded, and run a program correctly using this
> target and emulator??
> >yes
>
> Q2. Does your project include rts6400.lib??
> Check CCS 'Option->Customize->Program/Project/CIO' tab.
> >yes, I did.
>
> Q3. Is 'Do not Set CIO Breakpoint at Load' checked?? [it should NOT
be]
> >No.
>
> Q4. Is 'Do Not Set End of Program Breakpoint at Load' checked??
[it
> should NOT be]
> >No.
>
> Q5. Is 'Disable All Breakpoints When Loading New Programs' checked??
[it
> should NOT be]
> >No.
>
> Open a memory window in CCS at location 0x00006F60 while connected to
> the target.
> Change the contents to 0xAAAAAAAA and refresh the window.
> Q6. Does the window show 0xAAAAAAAA??
> >yes
>
> Change the contents to 0x55555555 and refresh the window.
> Q7. Does the window show 0x55555555??
> >yes
>
> This tells me that you hardware and emulator appear to be working.
> Your original error message indicates that there was problems setting
> or clearing a breakpoint. The simple exercise of reading and writing
> memory proved that it can be done [setting a sw breakpoint [BP]
> involves reading a memory location, saving the value, and writing a BP
> opcode into the memory location. The issue is compounded by CCS
> "helping you" when memory is displayed. If a location is known to have
> a BP, CCS shows you the original location contents instead of the
> actual location contents.
> My gut feeling is that there is a basic mistake that is being missed
> somewhere.
> Q1. What is your emulator's manufacturer name and model number??
> Do the following with CCS up:
> 1. reset the DSP
> 2. load the program. I assume that you will get a failure at 0x00006F60.
> 3. open the disassembly window if it is not open.
> 4. goto address 0x00006000 and highlight from there to 0x000070000.
> right click the highlighted block, select copy. then paste it into
> your reply.
> 5. open a memory window at 0x00006F60.
> 6. open a second memory window at 0x00046F60. I'm not sure if this
> will work-some c6x devices will 'mirror' the memory contents of
> internal memory. If this works, I expect all locations to be the same
> EXCEPT for 0x00006F60 & 0x00046F60. If this is true, copy the contents
> of 0x00046F60 and paste in your reply.
>
> mikedunn
>>
>> FYI-
>> The timing info will be misleading on an embedded system.
>> stdio on TI's embedded devices works something like this for each
>> stdio function [printf, time, etc]:
>> 1. A hidden BP is set using special label when the program is loaded.
>> 2. When the program is run, it halts at the BP.
>> 3. CCS polls the target for run or halt. If the program is halted,
>> CCS checks the label in the symbol table.
>> 4. If it is a stdio BP, CCS will read memory - I think it is the
>> first add after the BP. The add contains an opcode that indicates the
>> course of action.
>> 5 Once CCS 'does its duty' according to the opcode, a run command
is
>> issued to the target.
>> All of this makes stdio very s-l-o-w.
>>
>> mikedunn
>>>
>>> If the program runs, it can't go to the end. This problem has
>>> confused me for days. Any hints are welcome. Thank you in advance.
>>>
>>> Evironment:
>>> DM642, CCS3.3
>>>
>>> CODE:
>>> main.cmd
>>> MEMORY
>>> {
>>> IRAM: org = 0h, len = 10000h
>>> }
>>>
>>> SECTIONS
>>> {
>>> .data :> IRAM
>>> .text :> IRAM
>>> .switch :> IRAM
>>> .stack :> IRAM
>>> .bss :> IRAM
>>> .cinit :> IRAM
>>> .far :> IRAM
>>> .cio :> IRAM
>>> .const :> IRAM
>>> .sysmem :> IRAM
>>> .tables :> IRAM
>>> }
>>>
>>> main.c
>>>
>>> #include
>>> #include
>>>
>>> void main()
>>> {
>>> int j, a = 0;
>>> clock_t start, finish;
>>> double duration;
>>> start = clock();
>>> for (j = 0; j < 3; j++) {
>>> a += 1;
>>> }
>>> finish = clock();
>>> duration = (double)(finish -start) / CLOCKS_PER_SEC;
>>> printf("%f\n", duration);
>>> }
>>