"iarif" <108405@DSPRelated> writes:
>>"iarif" <108405@DSPRelated> writes:
>>
>>>>"iarif" <108405@DSPRelated> writes:
>>>>
>>>>>>>"iarif" <108405@DSPRelated> writes:
>>>>>>>
>>>>>>>>>"iarif" <108405@DSPRelated> writes:
>>>>>>>>>
>>>>>>>>>> Hi all, as you know, saturation arithmetic can be employed to
>>> avoid
>>>>>>>>>> overflow oscillations in discrete time systems. I want to know
>>> that
>>>>>>if
>>>>>>>> we
>>>>>>>>>> have calculated the saturation limit, how can the word-length
>>>>>>(number
>>>>>>>> of
>>>>>>>>>> bits) be calculated from this information? Is there any
> specific
>>>>>>>>>> relation?
>>>>>>>>>
>>>>>>>>>If you assume two's complement representation, the relationship
>>>>>>>>>is
>>>>>>>>>
>>>>>>>>> N >= log_2(MAX), unsigned
>>>>>>>>>
>>>>>>>>> N >= log_2(MAX) + 1, signed, including -MAX but excluding +MAX
>>>>>>>>>
>>>>>>>>> N >= log_2(MAX) + 2, signed, including -MAX and +MAX
>>>>>>>>>
>>>>>>>>>--
>>>>>>>>>Randy Yates
>>>>>>>>>Digital Signal Labs
>>>>>>>>>http://www.digitalsignallabs.com
>>>>>>>>
>>>>>>>> Does it imply that if saturation bound is +/-1 (as in case of
>>> global
>>>>>>>> saturation arithmetic to avoid overflow), no of bits chosen
> should
>>> be
>>>>>>>> greater than 2?
>>>>>>>
>>>>>>>Instead of asking us if Park Ave. is a one-way street south, try
>>> asking
>>>>>>>us how to get to Central Park.
>>>>>>>
>>>>>>>"overflow oscillations in discrete time systems" doesn't make any
>>> sense
>>>>>>>to me. Tell us what you're trying to do instead of asking for
>>>>>>>information on low-level operations. It also doesn't make any sense
>>> to
>>>>>>>ask about a saturation bound of +/- 1 for integers. So I'm afraid
> our
>>>>>>>semantic phase-lock is slipping quite a few degrees.
>>>>>>>--
>>>>>>>Randy Yates
>>>>>>>Digital Signal Labs
>>>>>>>http://www.digitalsignallabs.com
>>>>>>
>>>>> i am doing overflow oscillation elimination analysis in discrete
> time
>>>>> systems, which occur due to representation of number using fixed
> point
>>>>> arithmetic. I have applied saturation arithmetic as overflow
>>> correction
>>>>> technique. In my analysis, for a given disturbance energy (that
> occur
>>> in
>>>>> cascaded filters) and interference attenuation level, i have
>>> calculated
>>>>> (or got an idea) about saturation limit, such that under this
>>> saturation
>>>>> limit, overflow oscillations will be eliminated. For example, if we
>>> apply
>>>>> global saturation arithmetic property, the saturation bound is +/-1.
> So
>>> i
>>>>> want to know for some value of saturation bound, how i can calculate
>>> no
>>>>of
>>>>> bits
>>>>> (word-length) for implementation of digital filter.
>>>>> I hope my question makes sense now.
>>>>
>>>>A little more, thank you.
>>>>
>>>>I suggest you take a look at work already done by, e.g., [mitra],
> e.g.,
>>>>sections 9.10, "Reduction of Product Round-Off Errors Using Error
>>>>Feedback" and 9.11, "Limit Cycles in IIR Digital Filters" before
> trying
>>>>your own solutions (I believe the term "limit cycles" is what you are
>>>>referring to as "overflow oscillations). There are undoubtedly several
>>>>other sources as well.
>>>>
>>>>--Randy
>>>>
>>>>@BOOK{mitra,
>>>> title = "{Digital Signal Processing: A Computer-Based Approach}",
>>>> author = "Sanjit~K.~Mitra",
>>>> publisher = "McGraw-Hill",
>>>> edition = "second",
>>>> year = "2001"}
>>>>
>>>>--
>>>>Randy Yates
>>>>Digital Signal Labs
>>>>http://www.digitalsignallabs.com
>>>
>>> sir, thanku very much for your help. I have gone through such kind of
>>> topics earlier. Can you pls see the following paper
>>>
>>>
>>http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumbere08866&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F8920%2F4358609%2F06508866.pdf%3Farnumber%3D6508866
>>>
>>> I am doing such analysis. The saturation arithmetic employed in this
>>paper
>>> says that saturation limit is +/-1. My question is very simple. What
> does
>>> it mean by +/-1?. how can it be related to word-length?
>>
>>Without seeing the paper I am not sure I can give you a good answer.
>>However, many times in fixed-point arithmetic integers are scaled so
>>that their maximum magnitude is 1. For example, a 16-bit signed integer
>>scaled A(0, 15) (my notation from
>>
>> http://www.digitalsignallabs.com/fp.pdf
>>
>>) is related to its fixed-point value by
>>
>> x = X / 2^15,
>>
>>where x is the fixed-point value and X is the integer value. So, for
>>example, the negative full-scale of such an integer, -32678, is the
>>fixed-point value -1, and the positive full-scale of such an integer,
>>+32767, is +1 - 1 / 2^15 (just under +1).
>>
>>This scaling is easy to work with and is often used for that reason.
>>
>>So the answer is that the full-scale fixed-point value really can't
>>be related to word length, e.g., a full-scale value of +/- 1 could
>>be 16 bits, 32 bits, 64 bits, etc.
>>
>>What the wordlength determines is the resolution of the value
>>represented, and this is also related to the (fixed-point) round-off
>>error you can expect to get in the expected manner.
>>--
>>Randy Yates
>>Digital Signal Labs
>>http://www.digitalsignallabs.com
>
> Thanku, Your ans was very helpful :)
> So it implies that if i have chosen
> x = 1.2633
> X = 121
Where did these numbers come from? They make absolutely no sense
to me.
If you're using the notation I proposed above, then the scaling factor b
in a signed, fixed-point number that is scaled A(a,b) can be given
by
b = log_2(X / x)
and should be an integer. For your numbers,
b = log_2(121 / 1.2633)
= 6.58
Makes no sense.
> then no of bits required for hardware implementation is 8.
> Now, in case i want to represent my number 121 by 4 bits, and i apply
> rounding i.e
> 121 (decimal) = 01111001 (binary)
> after rounding to 4 bits = 0111 = 7 (decimal value)
> then does it mean that rounding error = 121-7 = 114?
I really have no idea what you are talking about. It seems we're not
really communicating.
--
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com