OK, I found the data sheet here:
http://www.analog.com/static/imported-files/data_sheets/AD6654.pdf
Look at PAACK, PBACK, and PCACK. It could be that adc data is controlled
by this and noise is not. Otherwise, if that is all you changed, I don't
see how you'd lose those control lines. The PDATA could all be zeros - so
that does not tell you anything. But PAIQ and PAREQ should tell you when
the data is clocking.
Check master/slave mode - maybe you accidently flipped a bit some where?
Doh! You have 0x44, 0x44, 0x44 - that turns on 6 channels. With 0x02,
0x02 0x02 you only turn on 3 channels. Try 0x22, 0x22, 0x22 and see what
happens.
Patience, persistence, truth,
Dr. mike
On Thu, 4 Mar 2010, Chew Swee Wan wrote:
> Hi Mike,
>
> I am helping Whim Min for this work.
>
> I need some explanation or clarification:
> When the AD6654 is in the internal Pseudo Random Noise generator mode
> (Address 0x0C to 0x0E with data 0x44,0x44,0x44), we have the PCLK, random
> digital outputs PADATA<15:0> and its related outputs, such as PAIQ, PAREQ
> (in Port A).
> We just change the data in the above Address to 0x02,0x02, 0x02
respectively
> for the ADC-in (AIN signal input), we have only PCLK, no more outputs
> PADATA<15:0>, PAIQ, PAREQ.
> I could not figure out how it is related to timing problem or are missing a
> pulse count some where, please help to explain to us.
> Special thanks.
>
> Best Regards,
> Swee Wan
>
> ==============================================> -----Original Message-----
> From: Mike Rosing [mailto:e...@eskimo.com]
> Sent: Tuesday, March 02, 2010 9:51 PM
> To: t...@stee.stengg.com
> Cc: a...
> Subject: Re: [adsp] Analog Device AD6654 in SPI Mode with Differential
> Inputs
>
> Can you hook up a processor of any kind with an spi port directly into the
> the AD6654? If so, compare the scope trace of the processor spi with the
> VHDL version. My bet is you have a timing problem or are missing a pulse
> count some where.
>
> Patience, persistence, truth,
> Dr. mike
> On Mon, 1 Mar 2010, t...@stee.stengg.com wrote:
>
>> Hi,
>>
>> I'm using Altera Stratix II to control the analog Device Part number
> AD6654(A mixed-signal IF-to-baseband receiver consisting of a 14-bit, 92.16
> MSPS analog-to-digital converter (ADC) and a 4-/6-channel, multimode
digital
> down-converter chip). I'm using VHDL to program the registers settings
in
> SPI mode for this chip. I'm only able to program on its internal test
signal
> (pseudo random test input signal) to generate an output signature in SPI
> mode.
>>
>> I had been trying very hard to generate an output signature with
> differential analog inputs AIN, but not successful. I had been trying with
> different registers setting with no results.
>>
>> Anybody who had use this chip or had a sample vhdl SPI code that can
> advise. Appreaciate very much.
>>
>> Whee Min
>>
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