Implementing IS-95, the CDMA Standard, on TMS320C6201 DSP
By Xiaozhen Zhang
IS-95 is the present U.S. 2nd generation CDMA standard. Currently, the 2nd generation
CDMA phones are produced by Qualcomm. Texas Instruments (TI) has ASIC design for Viterbi
Decoder on C54x. Several of the components in the forward link process are also implemented
in hardware. However, having to design a specific hardware for a particular application is
expensive and time consuming. Thus, the possibility of the alternative implementations is of
great interest to both customers and TI itself.
This research has achieved in successful implementation of IS-95 entirely in software on
TI fixed-point DSP TMS320C6201, and met the real time constraint. IS-95 system, the
industrial standard for CDMA, is a very complicated system and extremely computationally
demanding. The transmission rate for an IS-95 system is 1.2288 Mcps. This research project
includes all the major components of the demodulation process for the forward link system: PN
Descrambling, Walsh Despreading, Phase Correction & Maximal Ratio Combining,
Deinterleaver, Digital Automatic Gain Control, and Viterbi Deccc:r. The entire demodulation
process is done completely in C. That makes it a very attractive alternative implementation in
the future applications. It is well known that ASIC design is not only expensive and but also
time consuming, programming in assembly is easier and cheaper, but programming in C is a
much easier and efficient way out, in particular, for general computer engineers.
During the whole process, efforts have been devoted on developing various specific
techniques to optimize the design for all the components involved. These developments are
successfully achieved by making the best use of the following techniques: to simplify the
algorithms first before programming, to look for regularity in the problem, to work toward the
Compiler's full efficiency, and to use C intrinsics whenever possible. All these attributes together
make the implementation scheme great for DSP applications. The benchmark results compare
very well to the TI-internal hand scheduled assembly performance of the same type of decoders.
The estimated percentage usage of all the components (excluding PN) is only 21.18% of the total
CPU cycles available (4,000 K), which is very efficient and impressive.
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