Hybrid Floating Point Technique Yields 1.2 Gigasample Per Second 32 to 2048 point Floating Point FFT in a single FPGA

By Raymond J. Andraka

Abstract:

Hardware Digital Signal Processing, especially hardware
targeted to FPGAs, has traditionally been done using fixed
point arithmetic, mainly due to the high cost associated with
implementing floating point arithmetic. That cost comes in
the form of increased circuit complexity. The increase
circuit complexity usually also degrades maximum clock
performance. Certain applications demand the dynamic
range offered by floating point hardware, and yet require
the speeds and circuit density usually associated with fixed
point hardware. The Fourier transform is one DSP building
block that frequently requires floating point dynamic range.
Textbook construction of a pipelined floating point FFT
engine capable of continuous input entails dozens of
floating point adders and multipliers. The complexity of
those circuits quickly exceeds the resources available on a
single FPGA.
This paper describes a technique that is a hybrid of fixed
point and floating point operations designed to significantly
reduce the overhead for floating point. The results are
illustrated with an FFT processor that performs 32, 64, 128,
256, 512, 1024 and 2048 point Fourier transforms with
IEEE single precision floating point inputs and outputs.
The design achieves sufficient density to realize a
continuous complex data rate of 1.2 Gigasamples per
second data throughput using a single Virtex4-SX55-10
device.

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I have not worked with the Virtex4-SX55-10 device, but your article has given insights into thhybrid techniques of Floating and Fixed point DSP implementations.