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Sriyash Caculo (@sriyash_caculo)

Electronics and Instrumentation undergrad. GSoC'18 under FOSSi.

Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo August 13, 20181 comment

The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt.

The project overview was discussed in the previous blog posts. However this post serves as a guide to anyone who wishes to learn about the project or carry it forward. Hence I will go over the project details again.

Project overview

The project “Digital Filter Blocks in MyHDL and PyFDA integration" aims...


Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo July 9, 2018

This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks. 

So, why do we need to integrate and how do we go about it?

As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based...


Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo June 22, 2018

This blog post presents the progress made up to week 5 in my GSoC project “Digital Filter blocks and their integration in PyFDA”. Progress was made in two areas of the project.

  • Implementation of filter blocks in MyHDL
  • Design of interface between filter blocks and PyFDA

This post will primarily discuss filter block implementation. The interface will be discussed in a later post once further progress is made.

Direct form-I FIR filter

The equation specifies the direct form I...


Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo May 25, 20184 comments

Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus  pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing and its implementation on hardware.

This blog-post is the first of many to come for the...


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