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Re: Running Sum filter

Reply posted 1 year ago (01/27/2020)
Even though the ADC sampling frequency is 1.563Mhz, the maximum analog signal frequency that can be represented for 8 bit ADC is less than 5khz. It's not half the...

Re: Running Sum filter

Reply posted 1 year ago (01/27/2020)
I have few doubts. 1. I took Number of taps N= 2^14. I took that value after evaluating ADC with many values. How to decide number of taps for a particular sampling...

Re: Running Sum filter

Reply posted 1 year ago (01/27/2020)
Hello,Tracking ADC consist of three components. Comparator,  counter and DAC. External board consist of Comparator and DAC. Counter is implemented in FPGA. External...

Re: Running Sum filter

Reply posted 1 year ago (01/23/2020)
I’m sorry, Ill try to explain.I’m taking ADC reading for every 0.6µs(Fs=16MHz). This output is given to filter. Filter is running at 30MHz clock. So, it samples...

Re: Running Sum filter

Reply posted 1 year ago (01/22/2020)
Hi,@kazI took filter sampling frequency as 30Mhz. The maximum input signal frequency achieved is 35khz

Re: Running Sum filter

Reply posted 1 year ago (01/22/2020)
Hello,As I said in other post, the sampling frequency of 8-bit ADC is 1.563Mhz. For this, the SINAD and ENOB of ADC output achieved was ~37dB and ~5 bits respectively....

Re: Running Sum filter

Reply posted 1 year ago (01/21/2020)
Thank you for your response. I have a follow up question. Let's say that OW is just 8 bits instead of 14. Then according to your logic,  2^8 ie. 4^4 ..should turn...

Re: Running Sum filter

Reply posted 1 year ago (01/21/2020)
Hello,Thank you for the response. Sorry, I forgot to mention sampling frequency. ADC sampling frequency = 16Mhz.(Its not 1.563Mhz)Filter sampling frequency = 30Mhz.The...

Re: Moving average filter using Blockram

Reply posted 1 year ago (01/20/2020)
Hello Rick,I implemented running sum filter In FPGA.  Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator...

Running Sum filter

New thread started 1 year ago
Hello,I implemented running sum filter In FPGA.  Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator...

Re: Moving average filter using Blockram

Reply posted 1 year ago (12/08/2019)
Hi Rick,I implemented Tracking ADC on FPGA. I used LVDS pins as comparator. Actually, I'm oversampling but I don't understand why it's just 3khz.

Re: Moving average filter using Blockram

Reply posted 1 year ago (12/07/2019)
Hello Rick,I meant 0-3khz input signal to ADC. I will try to implement tap delay filter. Thank you for helping me!!!

Re: Moving average filter using Blockram

Reply posted 1 year ago (12/07/2019)
Hello Rick,You said that running sum filter is not right use. Could you please tell why it doesn't work?I thought of designing tap delay line filter as you suggested.But...

Re: Moving average filter using Blockram

Reply posted 1 year ago (12/06/2019)
Hello Richard,Thank you, I will read that article. Desired output signal bandwidth = 0 to 20khz or more than 20khz.If I take ADC sampling frequency as 1.563Mhz...

Re: Moving average filter using Blockram

Reply posted 1 year ago (12/06/2019)
Hi Richard Lyons,I wrote algorithm based on your answer. I understand you're busy but please reply when you find time. I'm really stuck with this. I implemented...

Re: Moving average filter using Blockram

Reply posted 1 year ago (12/06/2019)
Hello Richard Lyons,Thank you for the response. Please find the attached image. I implemented filter according to that equation. Should I divide the accumulator...

Re: Moving average filter using Blockram

Reply posted 1 year ago (12/06/2019)
Thank you for your answer. I'm trying to implement moving average filter using block ram which adds the current input and previous output, and then subtract the...

Moving average filter using Blockram

New thread started 1 year ago
Hello, I am trying to implement moving average filter using block ram. I have to filter the output of ADC. Sampling frequency of 8 bit ADC is 1.5Mhz. The ENOB for...

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