TDL for Parallel Processing
When multiplies and additions can be performed in parallel, the
computational complexity of a tapped delay line is
multiplies and
additions, where 
is the number of
taps. This computational complexity is achieved by arranging the
additions into a binary tree, as shown in Fig.2.21 for the
case 
.
 |
Next Section:
General Causal FIR Filters
Previous Section:
Transposed Tapped Delay Line
