Discrete-Time PLLs, Part 1: Basics
Still RelevantIntermediate
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
Summary
This tutorial introduces the fundamentals of discrete-time phase-locked loops (PLLs) with a focus on implementations in DSPs, FPGAs, and MATLAB. Readers will learn core building blocks (phase detector, loop filter, NCO), z-domain modeling, and practical considerations such as sampling, quantization, and implementation trade-offs.
Key Takeaways
- Describe the architecture and role of phase detector, loop filter, and numerically controlled oscillator in a discrete-time PLL
- Analyze stability and dynamic response using z-domain models and discrete-time transfer functions
- Implement core PLL blocks on DSPs/FPGAs and prototype them in MATLAB/Simulink
- Account for sampling, aliasing, quantization, and jitter when designing and tuning loop bandwidth
Who Should Read This
DSP and control engineers, FPGA/embedded developers, and graduate students who need to design or implement discrete-time PLLs for communications, radar, or real-time systems.
Still RelevantIntermediate
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