ADC Clock Jitter Model, Part 2 – Random Jitter
In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter. Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered...
Summary
This blog continues a practical examination of ADC sampling-time errors by modeling random clock jitter and its impact on converter performance. The author shows how to generate filtered and unfiltered random jitter in MATLAB, how it appears in the sampled-signal spectrum, and how it degrades SNR and measurement precision.
Key Takeaways
- Generate and apply filtered and unfiltered random clock jitter in MATLAB simulations of ADCs
- Quantify how random jitter degrades SNR and increases noise floor as a function of input frequency
- Analyze jitter effects in the frequency domain using PSDs and FFT/spectral plots
- Simulate Monte Carlo realizations to estimate statistical variability of ADC performance under jitter
- Interpret how jitter bandwidth and PSD shape influence measured spectral spurs and broadband noise
Who Should Read This
DSP engineers, test engineers, and researchers using MATLAB who need to model and quantify how random clock jitter affects ADC performance in communications, radar, or audio systems.
Still RelevantIntermediate
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