ADC Clock Jitter Model, Part 1 – Deterministic Jitter
Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2]. As shown in Figure 1, the ADC has a sample/hold...
Summary
Neil Robertson's blog analyzes deterministic sample-clock jitter in ADCs and its impact on sampled signals. The article derives a deterministic jitter model, links timing errors to spectral spurs and SNR degradation, and outlines measurement and simulation approaches for predicting ADC performance.
Key Takeaways
- Derive the deterministic jitter-induced error term in the sampled-signal model and relate it to time-domain sampling offsets.
- Relate jitter amplitude and tone frequency to spurious tones and harmonic content visible in FFT/spectral analysis.
- Estimate SNR degradation and spur levels for narrowband and wideband signals given clock-jitter parameters.
- Simulate deterministic clock-jitter effects in time-domain ADC models to reproduce and diagnose spectral spurs.
Who Should Read This
Intermediate-to-advanced DSP, RF, and system engineers designing or validating ADC-based communications, radar, or measurement receivers who need to model and mitigate deterministic clock jitter.
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