Decimators Using Cascaded Multiplierless Half-band Filters
In my last post, I provided coefficients for several multiplierless half-band FIR filters. In the comment section, Rick Lyons mentioned that such filters would be useful in a multi-stage decimator. For such an application, any subsequent multipliers save on resources, since they operate at a fraction of the maximum sample frequency. We’ll examine the frequency response and aliasing of a multiplierless decimate-by-8 cascade in this article, and we’ll also discuss an interpolator cascade using the same half-band filters.
Summary
This blog analyzes cascaded multiplierless half-band FIR filters applied to multistage decimation and interpolation, focusing on a decimate-by-8 cascade. The reader will learn how the cascade affects frequency response and aliasing, and how multiplierless stages reduce hardware resource use by shifting multipliers to lower-rate stages.
Key Takeaways
- Analyze the frequency response and aliasing behavior of a decimate-by-8 cascade of multiplierless half-band FIR filters.
- Estimate hardware resource savings by placing multipliers in lower-rate stages of a multistage decimator.
- Design an interpolator cascade using the same half-band filters to mirror decimation performance.
- Apply cascade and polyphase concepts to minimize computational load while preserving stopband attenuation.
Who Should Read This
Advanced/intermediate DSP engineers and FPGA/ASIC designers aiming to implement efficient multirate decimators or interpolators with minimal multipliers to reduce resource usage and control aliasing.
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