An FPGA Implementation of Hierarchical Motion Estimation for Embedded Oject Tracking
This paper presents the hardware implementation of an algorithm developed to provide automatic motion detection and object tracking functionality embedded within intelligent CCTV systems. The implementation is targeted at an Altera Stratix FPGA making full use of the dedicated DSP resource. The Altera Nios embedded processor provides a platform for the tracking control loop and generic Pan Tilt Zoom camera interface. This paper details the explicit functional stages of the algorithm that lend themselves to an optimised pipelined hardware implementation. This implementation provides maximum data throughput, providing real-time operation of the described algorithm, and enables a moving camera to track a moving object in real time.
Summary
This paper describes a hardware implementation of a hierarchical motion estimation algorithm for real-time object detection and tracking, targeted at an Altera Stratix FPGA. It explains the algorithmic stages that map efficiently to pipelined hardware, and shows how a Nios embedded processor is used for the tracking control loop and PTZ camera interface to enable moving-camera real-time tracking.
Key Takeaways
- Identify algorithm stages (coarse-to-fine hierarchical block matching) that are amenable to pipelined FPGA implementation
- Optimize the use of Altera Stratix dedicated DSP resources to maximize throughput for motion search kernels
- Integrate a Nios soft-core for the tracking control loop and pan-tilt-zoom (PTZ) camera interface to separate control and data-path tasks
- Design memory and streaming architectures to sustain real-time block-matching and full-frame throughput
- Evaluate resource vs. performance trade-offs to achieve real-time tracking with constrained FPGA logic and DSP blocks
Who Should Read This
FPGA/DSP engineers and system designers working on embedded video analytics or real-time tracking who need practical guidance mapping motion-estimation algorithms to FPGA hardware.
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