Designers of filters in FPGAs or ASICs may at times need to break their filter structure into two even/odd streams at half speed each but double resource. As there will be interdependency of the two streams, they need to model and verify that their structure works.
The code below shows that you can split the FIR coefficients into even/odd and split input into even/odd then create 4 filtered outputs(f1,f2,f3,f4) add them up as pairs into even/odd output then recombine. The key point is that f1,f2,f4 must be delayed one stage relative to f3
% odd/even filter structure verification % two filter structures compared % (1) direct use of filter function % (2) even/odd split structure x = randn(1,2048); h = fir1(23,.3); y1 = filter(h,1,x); % direct filter for reference he = h(1:2:end); % even coeff, relative to hardware definition ho = h(2:2:end); % odd coeffs xe = x(1:2:end); % even samples xo = x(2:2:end); % odd samples f1 = filter(ho,1,xe); %subfilter 1 f2 = filter(he,1,xo); %subfilter 2 f3 = filter(he,1,xe); %subfilter 3 f4 = filter(ho,1,xo); %subfilter 4 %add up subfilters, advancing f3 one stage ye = [0 f1] + [0 f2]; yo = [f3 0] + [0 f4]; %interleave even/odd into one stream y2 = [y1 0 0]; y2(1:2:end) = ye; y2(2:2:end) = yo; %quantise and compare both ref and subfilters y1 = round(y1*2^15); y2 = round(y2*2^15); plot(y1 - y2(2:end-1))