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Shai Kon (@Shaiko)


Re: Farrow Filter

Reply posted 2 months ago (04/06/2024)
weetabixharryYes, they are derived from the same XO on the board.My FPGA system clock is in the range of 300 MHz.So :1.The incoming samples should cross from the...

Re: Farrow Filter

Reply posted 2 months ago (04/05/2024)
Hi, I understand the concept but trying to achieve a better understanding how it would look in hardware. My goal is to implement the filter in hardware.

Re: Farrow Filter

Reply posted 2 months ago (04/05/2024)
So the architecture you have in mind clocks the ADC samples into h1,h2,h3,h4 using the ADC clock while the filters themselves together with the logic that calculated...

Farrow Filter

New thread started 2 months ago
Hello,As far as I understand the purpuse of a Farrow filter is to interpolate samples at a fractional ratio.For example: we have an ADC sampling at 41 MS/S and we...

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