Farrow Filter

Started by Shaiko 1 month ago19 replieslatest reply 3 weeks ago265 views


As far as I understand the purpuse of a Farrow filter is to interpolate samples at a fractional ratio.

For example: we have an ADC sampling at 41 MS/S and we need to transmit it using a DAC that expects 50 MS/S 

For an FPGA/ASIC engineer this clock domain crossing implies using some kind of buffering mechanism (i.e: asynchronous FIFO).

This FIFO will be written every cycles of the 41 MS/S side but read at the 50 MS/S side not every cycle to prevent underflow.

Because  of that, on the 50 MS/S side some samples (when the FIFO isn't read) would be used by the filter twice - which to my intuition feels "strange" because IMO all the 40 side samples should contribute equally to the generation of the interpolated 51 side samples.

Seems like there's something fundamentally incorrect in my understanding.

What am I missing ?

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Reply by SlartibartfastApril 5, 2024

This doesn't need to be a Farrow filter explicitly, but is essentially a polyphase filter resampling problem.   There are a lot of papers on this topic, and fred harris has a decent book on Multirate Signal Processing.   There are others as well.   This isn't a trivial topic, so you'll probably help yourself best by getting some of the good papers or books to use as a reference.

The filter would sit between your ADC and DAC.   The outputs of the ADC feed the filter, and the filter outputs feed the DAC.  The filter impulse response is synchronous to the output samples, i.e., the peak lobe of the filter response is always centered on an output sample.   The inputs get multiplied by the coefficients in the filter based on the time that they arrived relative to the peak of the filter response.

This is most easily done if you have a processing clock running Nx the output clock rate, so that you can clock a DDS/NCO accumulator with the Nx clock and use it to pick the coefficients from the filter, i.e., as time goes on and the phase counter increments, it can be used as an address progressing into the filter coefficient table.

There are other architectures depending on your constraints, but it can take thinking about this for a while to get the concepts if you are new to it.

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Reply by ShaikoApril 5, 2024


So the architecture you have in mind clocks the ADC samples into h1,h2,h3,h4 using the ADC clock while the filters themselves together with the logic that calculated the Delta work at a multiple of the DAC clock ?

Wouldn't we need a FIFO ? 

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Reply by SlartibartfastApril 5, 2024

The diagram isn't very good to show the issues, and imho to do the topic justice requires more than can be conveyed in an internet forum like this.   This is why I suggested you look at some of the existing literature and books, many of which include hardware architectures.   You might try starting with search terms like "polyphase filter resampler" or "multirate polyphase hardware" or something like that.   It's a topic that has a lot of detail that can change depending on requirements or preferences.

Your problem is not too different than a symbol rate synchronizer in a demodulator, where the output symbol rate may differ from the sampling rate.  That sort of thing is done in hardware all the time, and you may be able to find good references.  That is a case where using a DDS/NCO accumulator to set the output rate is pretty common.

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Reply by weetabixharryApril 6, 2024

@Slartibartfast Can you point to any specific literature you would recommend for a hardware (ASIC/FPGA) implementation?

The only helpful resource I have ever found on this topic (after considerable searching, over many years) is this:


It describes a software implementation, but one which is quite readily ported to digital hardware.

There seem to be countless books/articles covering traditional rational-ratio resampling (L/M where L and M are both small) but very little indeed covering "arbitrary" resampling (suitable for arbitrarily large and/or time-varying L and M).

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Reply by SlartibartfastApril 6, 2024

Well, crap.   I thought there were some useful references, and I've seen several good examples over the years, but you're right that it seems that not much pops up on a search these days.

Robert Adams published a paper on arbitrary audio resampling (which he and ADI were famous for years ago); A Monolithic Asynchronous Sample-Rate Converter for Digital Audio.  1993, but I don't know which exact journal.

Also search on anything "multirate" from fred harris.

Generally those don't get you to a clean description of an NCO/DDS-based arbitrary resampler, although that technique has been around for a long time as well, just not well published, evidently.  I know I've seen papers, but I can't find them now.

Jeebuz, maybe if I can make the time that'd be a good topic for another blog article.

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Reply by kazApril 6, 2024

This is an old paper from Altera (now Intel) about Farrow decimator implementation on FPGA. In your case you have Upsampler.


Also notice that if you just want upsampling 41 to 50 then don't worry about receiver symbol time tracking.

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Reply by kazApril 5, 2024

The clock crossing domain is not resampling. The two concepts are distinct.

Farrow filter are used for resampling. The critical parameter is the delay which will have its own algorithm. The delay and polyphase filters work out a new sample between adjacent samples. The net output is a resampled version which could be upsampling or downsampling sections for limited intervals. The ultimate result is a resampled stream. 

To grasp it better think of first order linear filter that just looks at two samples to get a new one in between. The system clock has to be high enough to follow the rate and from time a time a new samples emerges or a sample needs be dropped if delay exceeds one sample cycle. 

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Reply by ShaikoApril 5, 2024

Hi, I understand the concept but trying to achieve a better understanding how it would look in hardware. My goal is to implement the filter in hardware.

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Reply by kazApril 5, 2024

If 41 to 50 is fixed then resampling can be done either based on "fractional delay" method or could be done using "rational upsampling".

fractional delay method is best for symbol tracking at receivers. If using fractional delay method for fixed 41 to 50 then you need to convert the ratio of 41:50 to delay values.

rational upsampling is based on zero insertion (assumed) followed by filtering the images. This is much easier to understand but does not help receiver tracking as the ratio is variable unless you modify it to support variation at a cost. 

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Reply by engineer68April 8, 2024
Exactly, the non-matching frequencies do not automatically mean clock domain crossing. We first assume that the information is synchronized. Then a simple 50/41 ratio with an adapted CIC is suitable. If this is not the case, for example when a non-synchronized 48 kHz audio device is connected to a 44/48 kHz mixer, there is another problem to solve.  I once had to do this when I wanted to connect my E-MU Audity and Access Virus to my FPGA mixer. The solution was to synchronize the left input side to the source clock and then asynchronously pass the parameters of a constantly updated interpolation equation to the other side at any time and synchronize it there in the usual way. Together with the time, the target side could then use this equation to interpolate. It is then irrelevant whether the clocks jitter and even the edges change backwards briefly, which can be the case with almost identical frequencies. The equation always provides a meaningful value. This was essential for the EMU because it was running on the "same" frequency. However, I would not just interpolate linearly, but focus on 3 or 4 points and apply a correspondingly band-limited behavior.  Then the direct transformation to 96khz and others will also work. So does any input frequency - which was also required since the Virus used a non standard DAC frequency.
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Reply by napiermApril 30, 2024

If your sampling ratios are fixed, that is derived from the same clock, you may be able to do a rational re-sampler.  That is much easier than a Farrow filter and is much cleaner.

The thing about a Farrow filter is that it is very hard to get a good response from it at greater than 1/4 * Fs.  And that is for a good one say like a magnitude/derivative polyphase type.  A simpler 2nd or 3rd order one is much worse.  So you need to interpolate with the Farrow to 2X your output sample rate.  And then decimate back down with a half-band to clean up the garbage the Farrow adds above your designed pass-band.  The complexity depends on your needed frequency range.

Next thing is pulling the samples and generating the "mu" needed.  I've done this using a phase accumulator.  The value added to the accumulator is the ratio of input/output rate.  The upper bits of the accumulator give you "mu".  Every time the accumulator rolls over you pull another sample from the incoming domain.

Mark Napier

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Reply by weetabixharryApril 6, 2024


A key point that I think you may be missing is that sample rate and clock rate are not the same thing. The processing clock that clocks your resampler can (and often should) be totally different from your DAC (50 MHz) or ADC (41 MHz) sample rates.

For example, the processing clock in an FPGA implementation might be running at something like 600 MHz. In an ASIC, it may be even faster.

In many cases, it's a good idea for this clock frequency to be high, so your hardware multipliers are working at a high rate, so you need fewer of them. However, if you're not too worried about wasting some FPGA/ASIC resources (and you just want to get something working), then you could reduce this rate.

You can even reduce the clock rate below 50 MHz if you want to (and process the samples in parallel). This is almost certainly not the correct approach in this case, but I just want to be clear that it doesn't need to be tied to the DAC or ADC rate in any way.

So, like kaz said, it's extremely important to view the clock-crossing(s) as a completely separate issue to the sample rate conversion.

However, before you think about any of that, a much more fundamental issue is clock synchronization between the DAC and ADC clocks. You can clock your resampler however you want, but if the DAC and ADC clocks aren't derived from the same timing reference, then you're going to be in for a world of pain. Are your DAC and ADC sample clocks derived from a common reference?

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Reply by ShaikoApril 6, 2024


Yes, they are derived from the same XO on the board.

My FPGA system clock is in the range of 300 MHz.

So :

1.The incoming samples should cross from the ADC's 41 MHz domain to my system domain using a FIFO. The FIFO will be written every 41 MHz cycle and read on the 300 MHz side but not every cycle to prevent underflow.  

2.The Farrow Filter will be clocked at 300 MHz on the read side of that FIFO.

and would write the results into another FIFO.

3.The second FIFO will be read using the DAC clock.

Is this what you're suggesting ?

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Reply by weetabixharryApril 6, 2024

@Shaiko Yes, that would be a valid way of doing it. (And, most likely, it's how I would do it, depending on the exact requirements).

Technically, there may be ways to eliminate one or both of those FIFOs (or replace them with something cheaper). But in almost all cases, I would suggest to just use two FIFOs and only optimize resources later if absolutely necessary.

If you're not too worried about saving multipliers, then another option to consider would be to use 2 clocks instead of 3. In that case, your FPGA system clock would be driven by the 50 MHz DAC sample clock. In theory, that would increase you multiplier utilization by a factor of 6 (compared to a properly optimized design running at 300 MHz). But, in some cases, it might worth considering.

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Reply by SlartibartfastApril 6, 2024

If you have a very high processing clock relative to the sample clock, as you described, then a relatively easy way to get arbitrary resampling is to up-sample the input stream with a CIC filter to the highest rate that you can stand.   Then just take the closest output of the CIC interpolator (or most recent, if that works) to the sample instant of the desired output clock.

It's pretty easy to compute the maximum sampling jitter and error that this will create by comparing the rate of the CIC output to the desired output rate.

In your case, if you interpolate the 41 MHz signal up to the 300 MHz clock rate that you have available using a CIC interpolator, then taking every sixth output of that gives you a 50MHz output rate.   If the 300 MHz processing clock and the 50 MHz clock aren't synchronous, just take the nearest output of the 300 MHz clock at every 50 MHz clock edge.

If that gets you the performance you need that's a pretty easy solution since CIC are easy to build in an FPGA.  If the jitter/errors are too high with those relative rates, then a better polyphase (or whatever) solution may be needed.

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Reply by neiroberApril 6, 2024


You might find this classic paper helpful:

Gardner, F., "Interpolation in Digital Modems, Part 1: Fundamentals", IEEE Transactions on Communications", vol 41, no. 3, March 1993.  There is a free pdf version on the web (although the site is listed as not secure by Google).

- Neil

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Reply by SlartibartfastApril 6, 2024

That's one of the ones I was looking for!   It's still not the easiest read, but it does show using an NCO for selecting coefficients from a memory.   I put it on my site in case somebody needs it:


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Reply by neiroberApril 6, 2024

Here's a pdf of the Gardner paper:


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Reply by Jeremy35April 17, 2024
This is an older document from Altera (now Intel) discussing Farrow decimator implementation on FPGA. In your case, you're dealing with an upsampler. Additionally, if you only need to upsample from 41 to 50, there's no need to be concerned about receiver symbol time tracking.