Sriyash Caculo (@sriyash_caculo)
Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA
This Summer of Code project shows how to move from Python filter design to synthesizable HDL by building a MyHDL "filter-blocks" package and connecting it to PyFDA. The author implemented direct form I FIR and IIR blocks, added an API, tests, tutorials, and PyFDA export to VHDL and Verilog. The report also highlights practical fixed-point design choices and remaining work such as second-order sections.
Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA
This update shows a working integration between Pyfda and MyHDL using a compact API that passes fixed-point coefficients, stimulus data, and returns simulated filter responses. It walks through two usage styles, constructor-based and setter-method-based, and demonstrates a Pyfda workflow from specs to MyHDL simulation and plotting. Future plans include HDL code generation and API extension as filters grow.
Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA
By week 5 the project delivered parameterized MyHDL implementations of multiple digital filter topologies and started integration with PyFDA. The post walks through a behavioral direct-form I FIR, cascaded second-order-section implementations for FIR and IIR using structural modeling, and a parallel IIR design that concatenates per-section outputs for final summation. All designs infer order and coefficients from PyFDA, with examples in the filter-blocks repository.
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Sriyash Caculo is building a bridge between filter design and hardware by implementing digital filter blocks in MyHDL and integrating them with PyFDA as part of a Google Summer of Code project. The work aims to convert PyFDA floating point designs into fixed point MyHDL blocks that automatically generate VHDL or Verilog, with tests and tutorials to ensure correctness and usability.
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