Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash CaculoAugust 13, 20181 comment

The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt.

The project overview was discussed in the previous blog posts. However this post serves as a guide to anyone who wishes to learn about the project or carry it forward. Hence I will go over the project details again.

Project overview

The project “Digital Filter Blocks in MyHDL and PyFDA integration" aims to leverage and demonstrate the advantages of MyHDL, PyFDA and python in general in the field of Digital Filter design. MyHDL is a Python module for developing and testing HDL code.  PyFDA is a GUI based tool in written in Python/Qt for analysing and designing discrete time filters. The aim of the project is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based ‘filter-blocks’ package can automate both design and verification.

In order to realise the aim, it was necessary to build an API for the filter-blocks package which allows easy access to the filter implementations from external applications; or specifically in this case, Pyfda.

Further, linking MyHDL and PyFDA has more benefits. This combination could fill a gap in the open source tool chain between algorithm development and HDL fixpoint blocks.

Primary objectives

I had set out with a set of project goals in my introductory post of which most were realised in the prescribed time period and the rest are a work in progress.

These are the main milestones which were originally set:

  • Robust and rigorously tested implementation of multiple Digital Filter Blocks in MyHDL:
    • Direct form FIR filter.
    • Systolic implementation of linear phase FIR filter.
    • Parallel path implementation of IIR filter.
  • Tests for filter blocks to check correctness & performance.
  • Integration of the filters with PyFDA which would involve design of a suitable interface to pass filter coefficients to MyHDL filter blocks.
  • Tutorials and Documentation for all filter modules to improve usability.

During the course of the project, the main priorities of the project were established aided by discussions with my mentors. Building an API for the filter-blocks package was critical as it would serve the purpose of integration/communication with Pyfda, hence forming the backbone of the project. Along with the integration a few filter-implementations were necessary to test the integration.

The major milestones completed during the project (as of this post) are:

  • Built an API for the filter-blocks package to access all filter implementations and pass parameters. Tested the API with PyFDA for two filter implementations: Direct form I FIR filter and Direct form I IIR filter.
  • Filter implementations in filter-blocks package:
    • Direct form I FIR filter.
    • Direct form I IIR filter.
    • Parallel path implementation of IIR filter. [WIP]
    • Second order sections implementation of FIR/IIR filter. [WIP]
  • Tests for filter blocks to check correctness & performance.
  • Tutorial on how the use the API can be found here. The code has been documented with doctrings and comments to improve readability.

One of the biggest challenges during the course of the project were the hardware design choices for implementation of filters (especially IIR) in Myhdl. I found that even small changes in the design would have major implications on the final output and hence design choices had to be made carefully in order to get good correlation with the floating point implementations. The design choices which posed a challenge include deciding number of accumulator bits, adding saturation logic to the accumulator, truncating the accumulator in order to fit the output and feed-back, etc. 

Project Laundry List

Going into the technical aspect of my work done over the summer. Here I go over the work done till now by listing the merged pull requests and the work in progress. This may not be of interest to people who only want to know about Filter-blocks.

The following is the chronological list of commits/pull-requests along with a short description as to what functionality was added as a part of that commit:

(Merged) Commits

Fir direct form I implementation: Fir direct form I implementation along with tests in MyHDL.

IIR parallel implementation  : IIR parallel implementation along with tests in MyHDL.

Pyfda integration : Added support for filter-blocks integration in Pyfda.

Convert to vhdl or verilog in PyFDA : Added support to convert filter implementations to Verilog and VHDL in Pyfda.

Filter-blocks API and Filter implementations: This was a very large pull request which addresses different facets of the project.

API for the filter-blocks package was added for both FIR and IIR filters. Added setters and getters to pass parameters to the filter implementations and get output.

Further additions include direct form IIR implementation and tests. Tests to all the previous filter implementations have been reworked to now include calling filter implementations via newly designed API. The filter-implementations have also been tweaked and now include more parameters such as input signal bits, output signal bits.

API Tutorial : Added tutorials on how to use the filter blocks API.

(Work in Progress) Pull Requests

[WIP] Second order section filter and saturation logic for IIR filter : This PR focusses on fine tuning the IIR direct form implementation and adding support for second order sections implementation. Some broken tests in the previous PR are also being fixed.

In Conclusion

The previous blog posts related to this project are listed below:

Introductory Post

Update 1

Update 2

This post is incomplete without thanking my mentors Christopher Felton and Christian Muenker. They have been incredibly generous in giving me time and have been very encouraging throughout the course of the project. Dear mentors, It was a privilege for me to work with you and the Fossi community!

Previous post by Sriyash Caculo:
   Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA


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Comment by CaradocAugust 30, 2018

One problem of classic IIR implementation in FPGA is that you have a long combinational path. Hard to run them at 100 MHz (100 Msamples/s) or more for example. And you can't add pipeline delays without changing the transfer function.

I actually implemented scattered look-ahead IIR filters in the past , basically order-4 IIR filters with zero-pole cancellation so they would behave as an order-2 IIR filter.

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