DC Blocker Frequency Response
Figure B.11 shows the frequency response of the dc blocker
for several values of
. The same plots are given over a
log-frequency scale in Fig.B.12. The corresponding
pole-zero diagrams are shown in Fig.B.13. As
approaches
, the notch at dc gets narrower and narrower. While this may seem
ideal, there is a drawback, as shown in Fig.B.14 for the
case of
: The impulse response duration increases as
.
While the ``tail'' of the impulse response lengthens as
approaches
1, its initial magnitude decreases. At the limit,
, the pole and
zero cancel at all frequencies, the impulse response becomes an
impulse, and the notch disappears.
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Note that the amplitude response in Fig.B.11a and
Fig.B.12a exceeds 1 at half the sampling rate.
This maximum gain is given by
. In applications for
which the gain must be bounded by 1 at all frequencies, the dc blocker
may be scaled by the inverse of this maximum gain to yield
Next Section:
DC Blocker Software Implementations
Previous Section:
Allpass Filter Design




![\includegraphics[width=\twidth ]{eps/dcblockerfr}](http://www.dsprelated.com/josimages_new/filters/img1459.png)
![\includegraphics[width=\twidth ]{eps/dcblockerfrlf}](http://www.dsprelated.com/josimages_new/filters/img1460.png)
![\includegraphics[width=\twidth]{eps/dcblockerpz}](http://www.dsprelated.com/josimages_new/filters/img1461.png)
![\includegraphics[width=\twidth ]{eps/dcblockerir}](http://www.dsprelated.com/josimages_new/filters/img1462.png)



