Efficient arithmetic for high speed DSP implementation on FPGAs
The author was sponsored by EnTegra Ltd, a company who develop hardware and software products and services for the real time implementation of DSP and RF systems. The field programmable gate array (FPGA) is being used increasingly in the field of DSP. This is due to the fact that the parallel computing power of such devices is ideal for today’s truly demanding DSP algorithms. Algorithms such as the QR-RLS update are computationally intensive and must be carried out at extremely high speeds (MHz). This means that the DSP processor is simply not an option. ASICs can be used but the expense of developing custom logic is prohibitive. The increased use of the FPGA in DSP means that there is a significant requirement for efficient arithmetic cores that utilises the resources on such devices. This thesis presents the research and development effort that was carried out to produce fixed point division and square root cores for use in a new Electronic Design Automation (EDA) tool for EnTegra, which is targeted at FPGA implementation of DSP systems. Further to this, a new technique for predicting the accuracy of CORDIC systems computing vector magnitudes and cosines/sines is presented. This work allows the most efficient CORDIC design for a specified level of accuracy to be found quickly and easily without the need to run lengthy simulations, as was the case before. The CORDIC algorithm is a technique using mainly shifts and additions to compute many arithmetic functions and is thus ideal for FPGA implementation.
Summary
This PhD thesis investigates arithmetic techniques and architecture strategies for implementing high-speed DSP algorithms on FPGAs, with emphasis on resource-efficient cores for real-time tasks. Readers will learn how optimized arithmetic (fixed-point, redundant formats, pipelining) and hardware-aware algorithms (e.g., QR-RLS) enable MHz-rate adaptive filtering and RF/DSP processing without ASIC development costs.
Key Takeaways
- Evaluate trade-offs between fixed-point, block-floating and redundant arithmetic for FPGA DSP designs
- Apply pipelining, parallelization and resource-mapping techniques to accelerate QR-RLS and other adaptive-filter algorithms
- Design resource-efficient multiplier-accumulator and accumulator structures that exploit FPGA primitives (DSP slices, BRAM, LUTs)
- Estimate throughput, latency, and area for high-rate DSP cores and optimize for timing closure on modern FPGAs
- Adapt numerical algorithms (e.g., QR decomposition) to hardware-friendly forms to reduce cycles and improve robustness
Who Should Read This
FPGA and DSP engineers, researchers, or graduate students with experience in digital filter and adaptive algorithm design who need practical guidance on implementing high-throughput DSP (communications, radar, RF) on FPGAs.
Still RelevantAdvanced
Related Documents
- A New Approach to Linear Filtering and Prediction Problems TimelessAdvanced
- A Quadrature Signals Tutorial: Complex, But Not Complicated TimelessIntermediate
- An Introduction To Compressive Sampling TimelessIntermediate
- Lecture Notes on Elliptic Filter Design TimelessAdvanced
- Computing FFT Twiddle Factors TimelessAdvanced
