DSP Platform Benchmarking
Benchmarking of DSP kernel algorithms was conducted in the thesis on a DSP processor for teaching in the course TESA26 in the department of Electrical Engineering. It includes benchmarking on cycle count and memory usage. The goal of the thesis is to evaluate the quality of a single MAC DSP instruction set and provide suggestions for further improvement in instruction set architecture accordingly. The scope of the thesis is limited to benchmark the processor only based on assembly coding. The quality check of compiler is not included. The method of the benchmarking was proposed by BDTI, Berkeley Design Technology Incorporations, which is the general methodology used in world wide DSP industry. Proposals on assembly instruction set improvements include the enhancement of FFT and DCT. The cycle cost of the new FFT benchmark based on the proposal was XX% lower, showing that the proposal was right and qualified. Results also show that the proposal promotes the cycle cost score for matrix computing, especially matrix multiplication. The benchmark results were compared with general scores of single MAC DSP processors offered by BDTI.
Summary
This master's thesis benchmarks core DSP kernels on a single-MAC teaching processor using assembly-level implementations and the BDTI benchmarking methodology. Readers will learn how cycle counts and memory usage were measured, how results expose instruction-set strengths and weaknesses, and why specific FFT/DCT ISA enhancements were proposed.
Key Takeaways
- Measure cycle counts and memory usage of common DSP kernels using the BDTI benchmarking approach
- Assess the performance impact of a single-MAC instruction set on FFT, DCT and other DSP kernels
- Identify specific ISA changes that can accelerate FFT/DCT implementations
- Apply assembly-level benchmarking techniques to evaluate and compare DSP cores for teaching or embedded use
Who Should Read This
DSP engineers, graduate students, and architects with assembly-level interest who evaluate or design DSP processors and instruction sets for real-time audio, communications, or teaching platforms.
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