Implementation of Algorithms on FPGAs
This thesis describes how an algorithm is transferred from a digital signal processor to an embedded microprocessor in an FPGA using C to hardware program from Altera. Saab Avitronics develops the secondary high lift control system for the Boeing 787 aircraft. The high lift system consists of electric motors controlling the trailing edge wing flaps and the leading edge wing slats. The high lift motors manage to control the Boeing 787 aircraft with full power even if half of each motor’s stators are damaged. The motor is a PMDC brushless motor which is controlled by an advanced algorithm. The algorithm needs to be calculated by a fast special digital signal processor. In this thesis I have tested if the algorithm can be transferred to an FPGA and still manage the time and safety demands. This was done by transferring an already working algorithm from the digital signal processor to an FPGA. The idea was to put the algorithm in an embedded NIOS II microprocessor and speed up the bottlenecks with Altera’s C to hardware program. The study shows that the C-code needs to be optimized for C to hardware to manage the up speeding part, as the tests showed that the calculation time for the algorithm actually became longer with C to hardware. This thesis also shows that it is highly probable to use an FPGA equipped with Altera’s NIOS II safety critical microprocessor instead of a digital signal processor to control the electrical high lift motors in the Boeing 787 aircraft.
Summary
This thesis demonstrates how a high-performance DSP algorithm used for Boeing 787 high-lift motor control can be migrated from a dedicated DSP to an embedded microprocessor implemented in an FPGA using Altera's C-to-Hardware flow. Readers learn practical considerations for hardware/software partitioning, timing and safety validation, and performance trade-offs when implementing real-time control algorithms on FPGA-based soft processors.
Key Takeaways
- Evaluate the real-time feasibility of migrating a DSP algorithm to an FPGA-embedded microprocessor by measuring latency and worst-case execution time.
- Describe hardware/software partitioning strategies for moving compute-heavy functions into FPGA logic while keeping control and supervisory tasks on a soft-core processor.
- Apply the Altera C-to-Hardware toolchain and optimization techniques to convert C code into FPGA-accelerated logic blocks.
- Validate timing and safety requirements for motor control by performing timing analysis, resource estimation, and functional testing on the FPGA prototype.
- Estimate resource utilization and performance trade-offs (throughput, latency, fixed-point vs floating-point) when replacing a special-purpose DSP with an FPGA solution.
Who Should Read This
Embedded systems and control engineers (intermediate experience) who need to evaluate or execute migration of DSP/control algorithms from dedicated DSPs to FPGA-based microprocessors for real-time, safety-critical applications.
Still RelevantIntermediate
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