Summary

Neil Robertson's blog explains how to phase-lock a numerically controlled oscillator (NCO) to an external clock that is asynchronous to the system clocks, focusing on practical implementation in ASICs and FPGAs. It covers phase detector choices, discrete-time loop-filter design, clock-domain crossing strategies, and jitter/stability considerations engineers need to get a robust digital PLL working.

Key Takeaways

• Choose an appropriate digital phase detector architecture for asynchronous external clocks and NCO feedback.
• Design a discrete-time loop filter (z-domain) and set loop bandwidth and damping for stable lock and required tracking performance.
• Implement safe clock-domain crossing and interpolation methods to avoid metastability when sampling the external clock into system domains.
• Measure and mitigate jitter and phase noise; evaluate PLL stability margins and transient lock behavior in hardware.

Who Should Read This

FPGA/ASIC digital design and DSP engineers with intermediate-to-advanced experience who need to synchronize NCOs to external clocks for communications, radar, or real-time systems.

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