Hybrid Floating Point Technique Yields 1.2 Gigasample Per Second 32 to 2048 point Floating Point FFT in a single FPGA
Hardware Digital Signal Processing, especially hardware targeted to FPGAs, has traditionally been done using fixed point arithmetic, mainly due to the high cost associated with implementing floating point arithmetic. That cost comes in the form of increased circuit complexity. The increase circuit complexity usually also degrades maximum clock performance. Certain applications demand the dynamic range offered by floating point hardware, and yet require the speeds and circuit density usually associated with fixed point hardware. The Fourier transform is one DSP building block that frequently requires floating point dynamic range. Textbook construction of a pipelined floating point FFT engine capable of continuous input entails dozens of floating point adders and multipliers. The complexity of those circuits quickly exceeds the resources available on a single FPGA. This paper describes a technique that is a hybrid of fixed point and floating point operations designed to significantly reduce the overhead for floating point. The results are illustrated with an FFT processor that performs 32, 64, 128, 256, 512, 1024 and 2048 point Fourier transforms with IEEE single precision floating point inputs and outputs. The design achieves sufficient density to realize a continuous complex data rate of 1.2 Gigasamples per second data throughput using a single Virtex4-SX55-10 device.
Summary
This paper describes a hybrid floating-point FFT architecture that attains 1.2 Gigasample/s throughput for 32- to 2048-point transforms in a single FPGA by combining reduced-cost floating-point elements with high-throughput pipelining. Readers will learn the architectural techniques, resource/clock trade-offs, and implementation results that enable floating-point dynamic range at near fixed-point performance for real-time DSP applications.
Key Takeaways
- Describe a hybrid floating-point pipeline approach that reduces the number of full floating-point units while preserving dynamic range.
- Evaluate resource, latency, and clock-rate trade-offs for 32–2048 point FFTs implemented on a single FPGA at 1.2 GSa/s.
- Apply mapping strategies and pipelining techniques to implement continuous-stream, high-throughput FFT engines in FPGA fabric.
- Optimize arithmetic precision and scaling to balance numerical accuracy with logic and DSP utilization.
- Estimate applicability of the design to real-time communications and radar front-end processing where floating-point range is required.
Who Should Read This
FPGA and DSP system designers and engineers seeking high-throughput FFT implementations that require floating-point dynamic range while minimizing FPGA resource and timing cost.
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