TI F281x and F2833x ADC Configuration

Emmanuel February 17, 2011 Coded in C for the TI F28x

This piece of code contains a function which configures all the features of the ADC in TI F281x and F2833x families. In this case it uses a sample rate of 12.5 KHz and simultaneous sampling in channels A0 and B0. It is very simple to modify the code to change these parameters just by following the data sheet.

/**********************************************************************/
#include "DSP281x_Device.h"		//if using F2812
//#include "DSP2833x_Device.h" //if using F28335
/**********************************************************************
void InitAdc(void)
{
	
/*** ADC Reset*/

	AdcRegs.ADCTRL1.bit.RESET = 1;

	asm(" RPT #22 || NOP");		//Wait 2 clocks assuming ADCCLK=12.5 Mhz and SYSCLKOUT=150 Mhz
	
																			
/*** ADC Power-On	*/

	AdcRegs.ADCTRL3.all = 0x00ED;
			
// bit 15-9      0's:    reserved
// bit 8		 0:		 EXTREF
// bit 7-6       11:     ADCBGRFDN, Reference voltage, 00=off, 11=on
// bit 5         1:      ADCPWDN, Main Power Source, 0=off, 1=on
// bit 4-1       0110:   ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
// bit 0         1:      SMODE_SEL, 0=sequencial sampling, 1=simultaneous sampling

	DelayUs(5000);			//TI's asm function	
							//Wait 5 ms

/*** ADCMAXCONV	Register configuration*/

	AdcRegs.ADCMAXCONV.all = 0x0000;
	
// bit 15-7      0's:    reserved
// bit 6-4       000:    MAX_CONV2 
// bit 3-0       0000:   MAX_CONV1  (0 = 1 conversion)

/*** Select channels for sampling in SEQ1	*/

	AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0;	//Channels A0 and B0
		
/***  ADCTRL1 Register configuration	*/

	AdcRegs.ADCTRL1.all = 0x0700;
	
// bit 15        0:      reserved
// bit 14        0:      RESET
// bit 13-12     00:     SUSMOD, 00=ignore emulation suspend
// bit 11-8      0111:   ACQ_PS Acquisition window pre-scaler
// bit 7         0:      CPS Core clock
// bit 6         0:      CONT_RUN
// bit 5         0:      SEQ_OVRD
// bit 4         0:      SEQ_CASC
// bit 3-0       0000:   reserved

/*** ADCTRL2 Register configuration	*/

	AdcRegs.ADCTRL2.all = 0x0800;
	
// bit 15        0:      EVB_SOC_SEQ: SOC trigger by EVB
// bit 14        0:      RST_SEQ1: SEQ1 reset
// bit 13        0:      SOC_SEQ1: trigger signal for SEQ1
// bit 12        0:      reserved
// bit 11        1:      INT_ENA_SEQ1: SEQ1 interruption enable
// bit 10        0:      INT_MOD_SEQ1: interruption mode
// bit 9         0:      reserved
// bit 8         0:      EVA_SOC_SEQ1, 1=SEQ1 starts with EVA_SOC trigger
// bit 7         0:      EXT_SOC_SEQ1, 1=SEQ1 starts with ADCSOC input signal
// bit 6         0:      RST_SEQ2
// bit 5         0:      SOC_SEQ2
// bit 4         0:      reserved
// bit 3         0:      INT_ENA_SEQ2: SEQ1 interruption enabled
// bit 2         0:      INT_MOD_SEQ2: interruption mode
// bit 1         0:      reserved
// bit 0         0:      EVB_SOC_SEQ2

/*** ADC interruption enable	*/
PieCtrlRegs.PIEIER1.bit.INTx6= 1;	                 
IER |= 0x0001;              						

}

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