PhD in DSP underwater acoustics and optimal control Thales R&D in active/passive sonars SACET Research on Telecom Physical layers XILINX DSP expert covering half of Europe + India + Australia XILINX SW marketing for AI Engine (array of DSP processors)

Re: AD9601 with 200MSPS connected to DSP

Reply posted 2 years ago (05/16/2019)
I work for Xilinx! And I should have indicated it at the beginning.That's why I wrote in my first reply:So you have to interface the AD9601 onto an FPGA, preferably...

Re: AD9601 with 200MSPS connected to DSP

Reply posted 2 years ago (05/15/2019)
The problem I see is how to process a stream of samples @ 250Msps using a processor @180MHz.The FPGA should at least perform a downconversion.

Re: AD9601 with 200MSPS connected to DSP

Reply posted 2 years ago (05/15/2019)
Yes. Zynq parts are processors that have an FPGA part tightly coupled.https://www.xilinx.com/support/documentation/data_...https://www.xilinx.com/support/documentation/data_...These...

Re: AD9601 with 200MSPS connected to DSP

Reply posted 2 years ago (05/15/2019)
Hi Yash5,Not only you can use an FPGA but you have to!The AD9601 is a 200/250 Msps ADC, and the max clock rate of the stm32f429 is apparently 180MHz.So you have...

Re: Understanding the concept of Polyphase Filters

Reply posted 3 years ago (01/31/2019)
No you should use the figures on the right.The left figure on the downconversion encourage you to compute all the samples and then throw away M-1 out of M.The left...

Re: Understanding the concept of Polyphase Filters

Reply posted 3 years ago (01/31/2019)
The two filtering topology (before vs. after) gives exactly the same results in both upconversion and downconversion cases. So for your question about downsampling,...

Re: Folded FIR filter in Matlab or Octave

Reply posted 3 years ago (01/15/2019)
This architecture is valid just because your filter is symmetric.You gain a lot of time and resource when using specific architectures having a hardware Mult-Acc....

Re: Time domain signal slikes

Reply posted 3 years ago (01/15/2019)
Yes. Your Tx signal impinging on your Rx is very powerful compared to the signal coming back from the targets.

Re: Time domain signal slikes

Reply posted 3 years ago (01/15/2019)
Do you have the Tx functionning at the same time of the Rx?

Re: Fixed Point vs Floating Point

Reply posted 3 years ago (11/30/2018)
When the signal impinges on the input pin of the ADC, this is just an electric signal which voltage is between [-Vmax; +Vmax].This voltage is transformed into an...
If you want to stick with IIR, I would encourage you to look at Lattice Wave Digital Filters that have very good stability properties, and very narrow transition...
Yes, because this is the optimal way to behave in that case.
Hi Sumit,I think that the MRC isHence, when one branch is not available, its channel estimate is 0.Let say h2 is null, the equation reduces to:
The obvious answer is 3, but I think you have to add one more because the track on which the circle is moving is itself doing a rotation.So 4 should be the right...

Re: Implementing octave algorithm in FPGA using c++

Reply posted 3 years ago (06/18/2018)
Hi Abhinav90,apparently you want to use Vivado HLS so you should have a look to the User Guide 902 (UG902). Starting at page 614  (for the latest available version...

Re: Need help - Pink noise analyzer

Reply posted 3 years ago (06/04/2018)
Pink Noise has a spectral density that decreases in 1/f.so -10dB per octave

Re: Arbitrary Resampling issue : 30.72 MHz to 20 MHz

Reply posted 3 years ago (06/04/2018)
Kaz,It's true that if you take your filter example even a single multiplier is enough, running at 246.76MHz.I just had a look to the Channel filter specifications...

Re: Arbitrary Resampling issue : 30.72 MHz to 20 MHz

Reply posted 3 years ago (06/01/2018)
I don't know what is the target for this processing, but if it is an FPGA I would do this resampling task in multiple steps.125/192 = 5/4 x 5/4 x 5/12 = 5/6 x 5/4...

Re: Side lobes reduction after FFT

Reply posted 4 years ago (01/18/2018)
It's some kind of deconvolution algorithm.You identify the main peak, and then you remove from the FFT result everything that is related to this peak.One processing...

Re: IIR filters

Reply posted 4 years ago (11/29/2017)
As I said in my post, the linearity of the phase is something that you can handle by increasing slightly the IIR order. You can achieve easily an almost constant...

Re: IIR filters

Reply posted 4 years ago (11/29/2017)
I would say that implementation wise, when a FIR filter starts to have too many coefficients, an IIR is always a better solution. Typically when you start to think...

Re: fft/ifft scaling revisited

Reply posted 4 years ago (11/28/2017)
I think it is just a question of implementation efficiency.FFT followed by IFFT will end up in a unit gain transform.For N=2^n length transform, FFT and IFFT butterfly...

Re: Noise Generation Confusion

Reply posted 4 years ago (11/22/2017)
The error is in the computation of n:n = sqrt(np_watts/2)* ...because here you compute an amplitude, and the power of the complex number (Expectation) is 2.

Re: Frequency shifting with FFT

Reply posted 4 years ago (11/07/2017)
I forgot to add a lowpass filter as you are on the demodulation part, in order to remove the other part of the spectrum that goes at twice $$f_c$$

Re: Frequency shifting with FFT

Reply posted 4 years ago (11/07/2017)
Suppose your signal is $$s(nT)$$You want to shift it to the frequency $$f_c$$, the final signal will be $$y(nT)$$If you want to keep the complex signal: $$y(nT)...

Re: Frequency shifting with FFT

Reply posted 4 years ago (11/07/2017)
Why do you need an FFT for this?A simple digital mixer should be OK.

Re: DDS jitter

Reply posted 4 years ago (11/03/2017)
There are many parameters to this problem:FPGA clock jitterFrequency that is generatedoutput jitter is input jitter * fclk/f0  (fpga clock/generated clock frequency)Number...

Re: Differential encoder simulation

Reply posted 4 years ago (10/13/2017)
Typically when a[n-1] = 1, then the sgn(x[n]-a[n-1]) will be negative for x[n] less than 1.so for x[n] = 0.7 and a[n-1] = 1, sgn(x[n]-a[n-1]) = -1 even if x[n] is...
I would add that on hardware targets (FPGAs/ASICs) you are not limited to the clock rate of the device. You can create Super Sampling Rate architectures on which...

Re: Correct transfer function with 1st order IIR filter

Reply posted 4 years ago (08/16/2017)
The coefficients you are using are on the extreme limits of the possibilities of double precision floating point arithmetics.On double precision you have 53 bits...

Re: cascaded FFTs

Reply posted 4 years ago (07/10/2017)
Hi Amlangford,it is a little more complex than that.There are some weights before the second FFTI attached a pdf file that explains the method and 2 matlab files...

Re: Optimal Filter lineup selection

Reply posted 4 years ago (05/16/2017)
In general the criterion is more in the form of:- passband ripple is less than ...- stopband attenuation is more thanSeeing the downsampling ratio, a single DSP...

Re: PAPR (peak to average power ratio)

Reply posted 5 years ago (04/13/2017)
Usually OFDM signal (LTE kind:1280 carriers) have 12-13dB of PAPR. This PAPR has to be reduced in order to optimize the operating range of the Power Amplifier.Actually...

Re: DDC in FPGA with high speed ADC

Reply posted 5 years ago (04/10/2017)
Hi Mark,your approach is the right one (rotation FS/4, Half Band, rotation Fs/8, HalfBand), I wrote a little too fast at first place (and perhaps too late!). In...

Re: DDC in FPGA with high speed ADC

Reply posted 5 years ago (04/07/2017)
Hi Loganathan,you have to implement what we call a Super Sampling Rate architecture.So to speak, you have to process multiple samples in parallel.What I understand...

Re: Sampling frequency in Baseband

Reply posted 5 years ago (03/08/2017)
The second equation is the right one in terms of system bandwidth.You need to adapt the FFT length to the sampling rate in order to have:sampling_rate / number_of_bins...

Re: Decimation by 2

Reply posted 5 years ago (01/18/2017)
For sure I arrive far after all these nice answers. Downsampling by 2 using a half-band filter is very often (almost always) a good solution. The center tap is 1/2,...

Re: Sampling frequency in Baseband

Reply posted 5 years ago (10/12/2016)
Tim is correct.When your signal is real then you have to sample at least at twice the maximum frequency present in your signal. When the signal is complex (which...

Re: Test PLL against step change in phase

Reply posted 5 years ago (07/15/2016)
You're right. If you don't want a frequency offset you keep only:theta = offset;in=sin(2*pi*F*t+theta);And then you'll have your phase offset of theta.What is the...

Re: Test PLL against step change in phase

Reply posted 5 years ago (07/15/2016)
It all depends on the coefficients of your PLL. The code you give is just a way to create a sinusoid with a base frequency plus a frequency shift. In order to have...

Re: Pass band in digital up conversion of LTE signals

Reply posted 5 years ago (06/10/2016)
Hi LabPe43  (are you a cousin of C-3PO?),The signal to filter is complex and uses the band [-9MHz; 9MHz].The filter itself is real that's why we choose 9MHz of...

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