I am currently working on writing a scrambler and DeScrambler code for Orthogonal Frequency Division Multiplexing(OFDM). I am planning to write an algorithm for BPSK, QPSK and QAM scrambler-Descrambler before modulation and transmission. 

So far I have written an algorithm and test case  for BPSK and QPSK in Octave/Matlab and the code seems to work fine. Now I want to implement that in C++ so I can use Xilinx HLS to test my code on the FPGA for testing before I expand the algorithms.  The problem I am facing here is that I am quite new to C++ and feel more comfortable with Verilog and Sys Verilog but I have to write the codes in C++ for HLS to convert it into equivalent Hardware implementation:

Below is my Algorithm for the Scrambler in Octave, and if needed I can also provide the test case and code for DeScrambler.  Please check the queries after this code:

function [ScOutbits] = Scrambler(InputBits, BlockLen, ScramblerLUT)

   ScOutbits = [];

  switch (BlockLen)       % will be from test case usually either 1 or 2 depending on BPSK or QPSK

    case 1 %For BPSK, 1 bit per cyscle 

      state = [ 1 1 1 1 1 1 1]; % represents the 7 bit state shift register using LFSR 

      for k = 1:size(InputBits,2),

        xin = xor(state(4),state(7)); % polynomial used are x^7 and X^4 in this implementation

        state = [xin state(1:end-1)];

        ScOutbits(k) = xor(xin,InputBits(k));

      endfor

    case 2 % For QPSK, 2 bit per cycle 

      state = [ 1 1 1 1 1 1 1];

      for k = 1:1:size(InputBits,2)/BlockLen

        bit0 = InputBits(1,(k-1)*2+1);

        bit1 = InputBits(1,(k-1)*2+2);

        InputDataNum = 0;

        InputDataNum = bitset(InputDataNum,1,bit0);

        InputDataNum = bitset(InputDataNum,2,bit1);

        stateNum = 0;    

        for I21 = 1:1:7

        stateNum = bitset(stateNum,I21,state(1,7-I21+1));

        endfor

        LUTIdx = stateNum + bitshift(InputDataNum,7);

        LUTData =  ScramblerLUT(LUTIdx+1);

        ScOutbits((k-1)*2+1) = bitget(LUTData,8);

        ScOutbits((k-1)*2+2) = bitget(LUTData,9);

        state = state = [ bitget(LUTData,7) bitget(LUTData,6) bitget(LUTData,5) bitget(LUTData,4) bitget(LUTData,3) bitget(LUTData,2) bitget(LUTData,1) ];

      endfor 

  endswitch

** I have a few specific queries in this code snippet for C++:

* How should I implement the case 1 and Case 2 for loops in C++

* Is there any equivalent of bitset and bitget functions in C++ so I can get outbits 

Note: I have built a mask to extract 1 bits from an integer to be used as inputs like the seven bit for shift register [ 1 1 1 1 1 1 1], as there is no C++ equivalent of vectors in Octave. I am stuck thereon,

Hi Abhinav90,

apparently you want to use Vivado HLS so you should have a look to the User Guide 902 (UG902). Starting at page 614  (for the latest available version 2018.1) you have a description of the arbitary precision integer type ap_(u)int: all the functions and all teh redefined operators.

typically if you define a 7-bit integer like this:

ap_uint<7> State;

Then you can compute the next state by:

ap_uint<1> xin = State[4]^State[7]; // Bit Extraction (set or get) is the operator []

State = (State(6,0) , xin); // Concatenation is defined through the operator (high, low)

Hi oliviert,

Thanks for your reply, I am aware of that. The biggest problem I am facing is to how to retain the state of 2 bits when the blocklength is 2. I am trying to scramble multiple bits in the same cycle and I am unable to write equivalent C++ implementation like the octave code above. The bitset and bitget functions in Matlab/Octave make it easy to process multibits in same cycle but how to do the same thing in C++ is the problem for me. 

FYI: In last w days I have managed to write code for single bit per clock cycle in c++, I need to tweak that for 2 bits now 

Contact me oliviert@xilinx.com

Dear Abhinav90

I think you can convert MatLab to C++

See example:

Apologies I am quite off topic and wish you find your way but we can nowadays:

convert vhdl to circuit..

convert Verilog to circuit

convert System Verilog to circuit

convert vendor ips to HDL or netlist...

convert vendor simulink blocks to HDL...

convert Mathworks matlab to HDL

convert C to HDL

convert M files to C then HDL

Do we have to learn all these, aren't we flooded with products that appear just because others want to get rich. Is there any sympathy left for field designers?

You're right about that kaz. My reply is more informative

I believe the tools all there to ease the Research and Development process. In my personal experience I have felt that once a person becomes used to a particular language and it toolset then the algorithms are easy to develop and the thought process becomes synchronized to it. I maybe wrong but coming from Embedded and FPGA background I have felt it. It maybe different for software developers

The same way you can use: C, C++, Python, Compiled Python, Java, ... to program your processor.

The same question could be asked!

The thing is that each language suits better to somebody or somebody else and it's your own choice.

Now for Hardware design it is different: you perform 'hardware design' but you do 'processor programming', all these MATLAB, Simulink, C, C++ to HDL is just a way to allow much more people (software programmers) to design hardware because HDL requires so much different thinking.

Hi oswaldfontys,

I tried this tool in Matlab but it is providing very fuzzy logic and not at all doing what it's supposed to do

There is a tool called SystemC that converts C (and looks like C++) into a HDL form. See (the first couple of responses when googling "systemc")

http://www.asic-world.com/systemc/tutorial.html

http://www.asic-world.com/systemc/index.html

https://www.doulos.com/knowhow/systemc/tutorial/

I have not personally used this, but I know some who have and were very happy.

Hi mr_bandit,

I have a tool to convert C++ into Verilog through HLS, what I am looking to do is a way to convert octave/matlab algorithm into c++ with similar logic