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For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!
C-Compiler FPGA
Ariel Hernandez - Jun 15 2009
Hello Everybody!
I have a problem! I need a C-Compiler for a XILINX Spartan3E-500 FG320.
Can someone help me?
Vielen Dank!
... 
Test vectors and test procedures for FFT & DWT implemented on FPGA
umesh_sa1 - Jun 10 2009
Hi all,
If i implement a 1024 point FFT and 2D-DWT on some FPGA what are the important test vectors and test procedures i should carry out the same on the FPGA board. Any idea o... Book Needed on DSP Processors
oj_e...@yahoo.com - May 27 2009
Hey,
I am newbie in DSP HW design and need the following book.
VLSI digital signal processors: An introduction to rapid prototyping and design synthesis by V.K.Madisetti , IE... Recommendations on Floating Point C Evaluation Board w/ Sampler
tszu...@gmail.com - Mar 20 2009
Hello all,
I've been hunting the web for a DSP evaluation board with the following criteria:
1) Floating Point DSP Processor
2) C programming capabilities
3) On board sampler... Digital filters FPGA implementation [2 Articles]
grigoriou_i - Mar 9 2009
Greetings,
I have selected this topic for my dissertation topic and, since I have more of an Informatics background, I need some guidance. My only experience with FPGAs so far ... Inverse FFT Results
norw...@yahoo.com - Mar 5 2009
I will do my best to explain my problem clearly. I have this same problem using Labview, Matlab, and Scilab.
I start by building an array with three frequencies (f1,f2,and f3... Narrow band FIR filter [3 Articles]
rama...@gmail.com - Feb 16 2009
hi,
I am looking for Hardware/FPGA friendly FIR filter design.
The sampling rate is around 1250 MHz. FIR filter should be tunable with pass band of 5 MHz and cut-off of 2.5MHz ... Undersampling [3 Articles]
meht...@gmail.com - Feb 2 2009
I am amature to Software Defined Radios.
I am facing a problem regarding the selection of sampling frequency of ADC.
How to decide the sampling frequency so the carriers of diffe... FIR Filter Implementation in Verilog HDL
engi...@yahoo.com - Dec 3 2008
1) I need a simple to code in Verilog HDL for implementing a FIR Filter.
Filter equation is as under :
y[n] = 1/3(x[n] + x [n-1] + x[n-2]
2) Is there any book availaible for i... Need help in fft implementation on spartan 3 xilinx XC3S200 FPGA
harr...@gmail.com - Oct 13 2008
hi,
I am a student of M.Sc Electrical Engineering and for my Master's thesis i have to implement 256k point fft on spartan 3 xilinx XC3S200 FPGA. However, everyone who has worke...