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For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!
Downconverting several band segments
Justin Stocking - Aug 30 2011
Hello. I am building an FPGA based software radio.
It has a direct sampling ADC that then interfaces with the FPGA.
My ADC has a 50 mhz bandwidth, and I would like to selectively... 
Shaping with Farrow
niko...@yahoo.com - Mar 28 2011
Hello!
I wonder if there is any scientific paper on combining shaping filter (say typical SRRC) and Farrow filter that is used for rate matching?
I don't mean SRRC followed b... Signal Processing In FPGA [2 Articles]
Filipe - Mar 9 2011
Hi guys,
I am building a receiver and I will use FPGA to process the signal. My receiver has a front -end (antenna) a LNA, filter, and a A/D converter. After the A/D converter I... Fixed Point Averaging
kaly...@gmail.com - Dec 30 2010
Hi all,
I am working on an application which involves averaging of waveform records in FPGA.
Averaging of waveforms can be done by
1) storing intermediate presum and then f... FPGA Development Boards for Reconfigurable Computing
ahes...@gmail.com - Oct 18 2010
Hi! I am looking for FPGA Development Boards for Reconfigurable Computing applications. I want to make a project in this technology, but I don`t know which board to use.
My idea i... Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N)
gmdi...@gmail.com - May 13 2010
Hello,
Does somebody work with DC-VIDEO-TVP5146N Altera kit (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ?
I try to connect DC-VIDEO-TVP5146N to DK-NI... Designing a filter with low cut off and very high sampling rate
need...@yahoo.com - May 6 2010
Hi All,
I have to design a low pass bessel filter with bit rate of 100KHz. The cut off freq is .8* bit rate. The sampling frequensy is 100MHz. The output of the filter should se... An implementation of 20-points fft [4 Articles]
abhu...@yahoo.com - Apr 29 2010
Hello,
I'm new in the dsp world. I am doing a project that is about an implememtation of 20-points fft in vhdl.
** where I have decomposed N=2*2*5. I have already written radix-... Re:noise of DDC/DUC
cfel...@ieee.org - Apr 28 2010
Hi,thanks for reply.Do you mean SFDR of NCO in ddc module? if so ,I have tried to improve it,but it came out the same for output noise.
Yes/and no. You may need to explain ... Butterworth function vs. Bessel function [2 Articles]
needtolearnca - Apr 27 2010
Hi,
I am a logic designer new to the DSP area and I have a few basic questions regarding FIR/IIR filters. Any help/pointers is appreciated.
I read that FIR filters have no ...