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For engineers implementing DSP functions on FPGAs. This is a NEW Group that has just been created. It should take a few weeks before the group is big enough to become active. Please join!
pre amplifier, adc in spartan 3e kit
mura...@yahoo.co.in - Mar 10 2010
hi friends,
im using spartan 3e kit , and using the preamplifier and adc for analog capture, but when i see the output on chip scope there is a lot of noise...
the input a... 
xps_adc delta sigma
atlantis2886 - Jan 30 2010
Hello
I am a beginner using FPGA. I make use of EDK. My question is with regards to the xps_deltasigma adc, it is supposed to convert an analog signal to its digital counterpa... Digital Filter (variable sampling rate)
jaso...@gmail.com - Jan 15 2010
Hi. How to design a digital filter that can respond to variable sampling rate?
Any guide or good article on it? Pls recommend.
thanks
... Half band interpolating by 2 FIR not appropriate? [2 Articles]
alek...@gmail.com - Jan 6 2010
Hi,
I am trying to design Half Band Interpolating by 2 FIR, something that should be straight forward, however, I came across the problem that raises suspicion. Since the filter... interfacing ADAU1701 with controller/FPGA
ramm...@ymail.com - Dec 20 2009
hi..
I would like to know about the interfacing of ADAU 1701 with any microcontroller(eg:STM32F).
In my current project speaker management system (to control parameters l... THD+N Asin (wt)
jaso...@gmail.com - Dec 18 2009
Hi. I generated 1 sine wave(24bit output[23:0]). In order to control the amplitude, the output multiply with a ratio(fixed point multiplier). for fix point multiplication,
v... choices, choices?
skun...@yahoo.co.uk - Nov 2 2009
i,m dyslexic so please bare with me.....
i,m looking to buy a dsp or fpga(DSP) that excels in the following qualities:
1. a/d d/a conversion 0.01hz or dc to 100hz ELF spectrum.
... FIR Filter Implementation in Verilog HDL [4 Articles]
engi...@yahoo.com - Oct 27 2009
1) I need a simple to code in Verilog HDL for implementing a FIR Filter.
Filter equation is as under :
y[n] = 1/3(x[n] + x [n-1] + x[n-2]
2) Is there any book availaible for i... Direct route
bigbibby2002 - Sep 30 2009
hi, I'm puzzled that is there method implementing the pin-to-pin connection in FPGA or CPLD.it means there is no buffer on the route.
It act as a wire that connets two pins on ... Analysis for a FFT implementation in FPGA
Iván_Marote_Álvarez - Sep 25 2009
Hi,
I would like to know some references about how to implement
the FFT algorithms in a FPGA and the challenges that it involves,
I mean, complexity, memory, timing,...
I'...