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Hi Ajith, first of all, here is a neat little trick -- when setting up TCBs for SPORT DMA, save memory and setup only the 5 words that are used by the internal DMA (EI, EM EC are unused and will not be loaded): //------ Transmit ----------------------- // Initialisers are: GP, CP, C, IM, II .var tx_tcb0_sport1[5] = {0, tx_tcb1_sport1+4-0x08000, 8, 1, SPort1TxBuffer0}; .var tx_tcb1_sport1[5] = {0, tx_tcb2_sport1+4-0x08000, 8, 1, SPort1TxBuffer1}; .var tx_tcb2_sport1[5] = {0, tx_tcb3_sport1+4-0x08000, 8, 1, SPort1TxBuffer2}; .var tx_tcb3_sport1[5] = {0, tx_tcb0_sport1+4-0x08000, 8, 1, SPort1TxBuffer3}; When starting the DMA chain, I let the core execute this: // ----- start SPort0 DMA ----- r1 = tx_tcb0_sport0+4-0x8000; // write address of tcb to chain pointer to start dma dm(DSP21065L_CPT0A) = r1; As you can see, the TCB register ordering is reversed, and the chain pointer must adress the last adress of the next TCB since chain loading starts from internal index backwards (see table on page 6-41; you did this right). I do not offset the adresses of the DMA data buffers, contradicting the 3rd paragraph on page 6-28; it is used this way in the example on page 9-94 and in several demo programs from ADI itself. -- And I do not change anything for simulator vs. emulator... All of this seems to work, but re-reading page 6-28 ff. of the Users Manual gets me a little bit confused, too. I remember asking our lokal ADI FAE for advice on wich registers need to be offset, and he told me use this setup. My thoughts on this: If a register needs to be offset by -0x8000 (that is, the offset of 0x8000 is internally added), but you do not subtract it from your 'real world' adress, I think the DMA controller will get a carry to bit 16 when adding 0x8000 a second time. This will move your adress to the corresponding short word adress, and your DMA would only transfer 16 bits per access from/to memory. If you handle only 16 bit values through SPORT DMA, this may even work well, but since you get a 16 bit (single column) memory access stride I think you would experience weird effects otherwise... ;) I do not know what will happen when doing the offset on a register that really does not need it. Maybe I should re-evaluate all of this to be sure what I'm really doing. So long Friedrich -----Ursprgliche Nachricht----- Von: Ajith Kumar P C [mailto:] Gesendet: Dienstag, 10. Juni 2003 08:54 An: Burgwedel, Friedrich; Betreff: Re: AW: AW: [adsp] Re: Simulate External devices on vdsp dear Friedrich I am afraid that i am doing wrong. i am also working in 21065l, and i am not doing any offset for DMA chain pointer in real time (not in simulation or emulation). This is the code for TCB initialization for the SPORT DMA (which i am using) xmit_tcb[7] = (int)tx_buff; // internal dma address xmit_tcb[6] = 1; // internal modifier xmit_tcb[5] = 5; //8 // internal count xmit_tcb[4] = (((int)&xmit_tcb[7])&0x0001ffff)|0x00020000; // set the pci bit on transmit block chain pointer xmit_tcb[3] = 0; xmit_tcb[2] = 0; xmit_tcb[1] = 0; xmit_tcb[0] = 0; For the simulation the xmit_tcb[7] is as follows xmit_tcb[7] = (int)tx_buff - 0x8000; // internal dma address On simulation time i changed the xmit_tcb[7] only. The rest r the same. I am confused, since i am getting realtime data with this initialization. pls expalin ur method and if possible give ur TCB initialization routine for my understanding. regards ajith --- "Burgwedel, Friedrich" <> wrote: > > I had done the chained SPORT DMA in our board. it > > is working perfectly without any offsetting. > > Yes, the index register is used without offset, but > the DMA chain pointer > register needs the offset. (21065L) > > Friedrich > > -----Ursprgliche Nachricht----- > Von: Ajith Kumar P C [mailto:] > Gesendet: Freitag, 6. Juni 2003 15:28 > An: Burgwedel, Friedrich; > Betreff: Re: AW: [adsp] Re: Simulate External > devices on vdsp __________________________________ |
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DMA setup, was: Simulate External devices on vdsp
Started by ●June 10, 2003
Reply by ●June 10, 20032003-06-10
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Hi Friedrich Thanks for ur direction. I too get confused. I tried the data transfer through SPORT both on simulation and real time hardware environment. It is 32 bit data transfer. I put the sine wave as input (actually CODEC is connected to the SHARC) and stores the data acquired in some buffers. I cross checked the input and output values. It is the same. Also I am able to retransmits the acquired data through the CODECs output channel. Here I am not offsetted any of the DMA parameter registers. I tried this in simulation environment also. At the very first time I hadnt get any data at the DMAs receive buffers. So as u confused with 6-28 details, I offsetted the index register with 0x8000 for simulation purpose and tested the receive buffer. (the whole project is compiled with out any error but it shows the warning as warning #170-D: pointer points outside of underlying object xmit_tcb[7] = (int)tx_buff-0x8000;// internal dma address). But the data received is correct on simulation by this change. I posted this weird behavior of the simulator in adsp group (message number 1365). Later I found the possible cause of this weird behavior from the ADI s anomaly list. I am copying here for easy reference. I am using VDSP release 2.0 for the above simulation and the processor is 21065L. ********************************************* 9268: 21065 simulator not handling DMA Registers:IIx, IMx, CPx DSP Family: SHARC First Discovered in: VDSP++ 2.0 Tool: Simulator Prognosis: Fixed in an upcoming release (Hot fix available: sharc_simulator_2.3.0.18_20030401.zip or later) In the 2.0 release of the 21065L simulator, the simulator is not handeling the following registers correctly: IIx, IMx, CPx Unlike the rest of the 2106x family, where these registers are "offsets" from the start of internal memory, in the 21065L they are "absolute" addresses. The simulator is incorrectly treating them as offsets. This issue will be fixed in the VisualDSP++ 3.0 SHARC release. ************************************************** Anyway I will again cross check my Real Time program and the data acquired. The Simulation process I checked now, I had configured the parameter registers with the same value what I had explained in earlier postings and the data transfer is checked with streaming. It gives correct result. regards ajith --- "Burgwedel, Friedrich" <> wrote: > Hi Ajith, > > first of all, here is a neat little trick -- when > setting up TCBs for SPORT > DMA, save memory and setup only the 5 words that are > used by the internal > DMA (EI, EM EC are unused and will not be loaded): > > //------ Transmit > ----------------------- > // Initialisers are: GP, CP, C, IM, II > .var tx_tcb0_sport1[5] = {0, > tx_tcb1_sport1+4-0x08000, 8, 1, > SPort1TxBuffer0}; > .var tx_tcb1_sport1[5] = {0, > tx_tcb2_sport1+4-0x08000, 8, 1, > SPort1TxBuffer1}; > .var tx_tcb2_sport1[5] = {0, > tx_tcb3_sport1+4-0x08000, 8, 1, > SPort1TxBuffer2}; > .var tx_tcb3_sport1[5] = {0, > tx_tcb0_sport1+4-0x08000, 8, 1, > SPort1TxBuffer3}; > > When starting the DMA chain, I let the core execute > this: > > // ----- start SPort0 DMA ----- > r1 = tx_tcb0_sport0+4-0x8000; // write address of > tcb to chain pointer to > start dma > dm(DSP21065L_CPT0A) = r1; > > As you can see, the TCB register ordering is > reversed, and the chain pointer > must adress the last adress of the next TCB since > chain loading starts from > internal index backwards (see table on page 6-41; > you did this right). > > I do not offset the adresses of the DMA data > buffers, contradicting the 3rd > paragraph on page 6-28; it is used this way in the > example on page 9-94 and > in several demo programs from ADI itself. -- And I > do not change anything > for simulator vs. emulator... > > All of this seems to work, but re-reading page 6-28 > ff. of the Users Manual > gets me a little bit confused, too. I remember > asking our lokal ADI FAE for > advice on wich registers need to be offset, and he > told me use this setup. > > My thoughts on this: > > If a register needs to be offset by -0x8000 (that > is, the offset of 0x8000 > is internally added), but you do not subtract it > from your 'real world' > adress, I think the DMA controller will get a carry > to bit 16 when adding > 0x8000 a second time. This will move your adress to > the corresponding short > word adress, and your DMA would only transfer 16 > bits per access from/to > memory. If you handle only 16 bit values through > SPORT DMA, this may even > work well, but since you get a 16 bit (single > column) memory access stride I > think you would experience weird effects > otherwise... ;) > I do not know what will happen when doing the offset > on a register that > really does not need it. > > Maybe I should re-evaluate all of this to be sure > what I'm really doing. > > So long > Friedrich > > -----Ursprgliche Nachricht----- > Von: Ajith Kumar P C [mailto:] > Gesendet: Dienstag, 10. Juni 2003 08:54 > An: Burgwedel, Friedrich; > Betreff: Re: AW: AW: [adsp] Re: Simulate External > devices on vdsp > dear Friedrich > I am afraid that i am doing wrong. i am also > working in 21065l, and i am not doing any offset for > DMA chain pointer in real time (not in simulation or > emulation). This is the code for TCB initialization > for the SPORT DMA (which i am using) > > xmit_tcb[7] = (int)tx_buff; // > internal dma address > xmit_tcb[6] = 1; > // internal modifier > xmit_tcb[5] = 5; //8 // > internal count > xmit_tcb[4] = > (((int)&xmit_tcb[7])&0x0001ffff)|0x00020000; // set > the > pci bit on transmit block chain pointer > xmit_tcb[3] = 0; > xmit_tcb[2] = 0; > xmit_tcb[1] = 0; > xmit_tcb[0] = 0; > > For the simulation the xmit_tcb[7] is as follows > xmit_tcb[7] = (int)tx_buff - 0x8000; // internal dma > > address > On simulation time i changed the xmit_tcb[7] only. > The > rest r the same. > > I am confused, since i am getting realtime data with > this initialization. pls expalin ur method and if > possible give ur TCB initialization routine for my > understanding. > > regards > ajith > > --- "Burgwedel, Friedrich" <> > wrote: > > > I had done the chained SPORT DMA in our board. > it > > > is working perfectly without any offsetting. > > > > Yes, the index register is used without offset, > but > > the DMA chain pointer > > register needs the offset. (21065L) > > > > Friedrich > > > > -----Ursprgliche Nachricht----- > > Von: Ajith Kumar P C [mailto:] > > Gesendet: Freitag, 6. Juni 2003 15:28 > > An: Burgwedel, Friedrich; > > Betreff: Re: AW: [adsp] Re: Simulate External > > devices on vdsp > __________________________________ > __________________________________ |
Reply by ●June 10, 20032003-06-10
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Hi Ajith, thx for your valuable information. I too will x-check my code and change/test all my DMA pointers; but I wonder why DMA chaining works with my hardware when using chain pointers as offsets, when ADI tells us these pointers are absolute on the 21065L. It's quite a mystery to me... Thanks for 'pressing your thumb on the spot'! So long Friedrich -----Ursprgliche Nachricht----- Von: Ajith Kumar P C [mailto:] Gesendet: Dienstag, 10. Juni 2003 16:09 An: Burgwedel, Friedrich; Betreff: Re: [adsp] DMA setup, was: Simulate External devices on vdsp Hi Friedrich Thanks for ur direction. I too get confused. I tried the data transfer through SPORT both on simulation and real time hardware environment. It is 32 bit data transfer. I put the sine wave as input (actually CODEC is connected to the SHARC) and stores the data acquired in some buffers. I cross checked the input and output values. It is the same. Also I am able to retransmits the acquired data through the CODEC's output channel. Here I am not offsetted any of the DMA parameter registers. I tried this in simulation environment also. At the very first time I hadn't get any data at the DMA's receive buffers. So as u confused with 6-28 details, I offsetted the index register with 0x8000 for simulation purpose and tested the receive buffer. (the whole project is compiled with out any error but it shows the warning as "warning #170-D: pointer points outside of underlying object xmit_tcb[7] = (int)tx_buff-0x8000;// internal dma address"). But the data received is correct on simulation by this change. I posted this weird behavior of the simulator in adsp group (message number 1365). Later I found the possible cause of this weird behavior from the ADI 's anomaly list. I am copying here for easy reference. I am using VDSP release 2.0 for the above simulation and the processor is 21065L. ********************************************* 9268: 21065 simulator not handling DMA Registers:IIx, IMx, CPx DSP Family: SHARC First Discovered in: VDSP++ 2.0 Tool: Simulator Prognosis: Fixed in an upcoming release (Hot fix available: sharc_simulator_2.3.0.18_20030401.zip or later) In the 2.0 release of the 21065L simulator, the simulator is not handeling the following registers correctly: IIx, IMx, CPx Unlike the rest of the 2106x family, where these registers are "offsets" from the start of internal memory, in the 21065L they are "absolute" addresses. The simulator is incorrectly treating them as offsets. This issue will be fixed in the VisualDSP++ 3.0 SHARC release. ************************************************** Anyway I will again cross check my Real Time program and the data acquired. The Simulation process I checked now, I had configured the parameter registers with the same value what I had explained in earlier postings and the data transfer is checked with streaming. It gives correct result. regards ajith --- "Burgwedel, Friedrich" <> wrote: > Hi Ajith, > > first of all, here is a neat little trick -- when > setting up TCBs for SPORT > DMA, save memory and setup only the 5 words that are > used by the internal > DMA (EI, EM EC are unused and will not be loaded): > > //------ Transmit > ----------------------- > // Initialisers are: GP, CP, C, IM, II > .var tx_tcb0_sport1[5] = {0, > tx_tcb1_sport1+4-0x08000, 8, 1, > SPort1TxBuffer0}; > .var tx_tcb1_sport1[5] = {0, > tx_tcb2_sport1+4-0x08000, 8, 1, > SPort1TxBuffer1}; > .var tx_tcb2_sport1[5] = {0, > tx_tcb3_sport1+4-0x08000, 8, 1, > SPort1TxBuffer2}; > .var tx_tcb3_sport1[5] = {0, > tx_tcb0_sport1+4-0x08000, 8, 1, > SPort1TxBuffer3}; > > When starting the DMA chain, I let the core execute > this: > > // ----- start SPort0 DMA ----- > r1 = tx_tcb0_sport0+4-0x8000; // write address of > tcb to chain pointer to > start dma > dm(DSP21065L_CPT0A) = r1; > > As you can see, the TCB register ordering is > reversed, and the chain pointer > must adress the last adress of the next TCB since > chain loading starts from > internal index backwards (see table on page 6-41; > you did this right). > > I do not offset the adresses of the DMA data > buffers, contradicting the 3rd > paragraph on page 6-28; it is used this way in the > example on page 9-94 and > in several demo programs from ADI itself. -- And I > do not change anything > for simulator vs. emulator... > > All of this seems to work, but re-reading page 6-28 > ff. of the Users Manual > gets me a little bit confused, too. I remember > asking our lokal ADI FAE for > advice on wich registers need to be offset, and he > told me use this setup. > > My thoughts on this: > > If a register needs to be offset by -0x8000 (that > is, the offset of 0x8000 > is internally added), but you do not subtract it > from your 'real world' > adress, I think the DMA controller will get a carry > to bit 16 when adding > 0x8000 a second time. This will move your adress to > the corresponding short > word adress, and your DMA would only transfer 16 > bits per access from/to > memory. If you handle only 16 bit values through > SPORT DMA, this may even > work well, but since you get a 16 bit (single > column) memory access stride I > think you would experience weird effects > otherwise... ;) > I do not know what will happen when doing the offset > on a register that > really does not need it. > > Maybe I should re-evaluate all of this to be sure > what I'm really doing. > > So long > Friedrich > > -----Ursprgliche Nachricht----- > Von: Ajith Kumar P C [mailto:] > Gesendet: Dienstag, 10. Juni 2003 08:54 > An: Burgwedel, Friedrich; > Betreff: Re: AW: AW: [adsp] Re: Simulate External > devices on vdsp > dear Friedrich > I am afraid that i am doing wrong. i am also > working in 21065l, and i am not doing any offset for > DMA chain pointer in real time (not in simulation or > emulation). This is the code for TCB initialization > for the SPORT DMA (which i am using) > > xmit_tcb[7] = (int)tx_buff; // > internal dma address > xmit_tcb[6] = 1; > // internal modifier > xmit_tcb[5] = 5; //8 // > internal count > xmit_tcb[4] = > (((int)&xmit_tcb[7])&0x0001ffff)|0x00020000; // set > the > pci bit on transmit block chain pointer > xmit_tcb[3] = 0; > xmit_tcb[2] = 0; > xmit_tcb[1] = 0; > xmit_tcb[0] = 0; > > For the simulation the xmit_tcb[7] is as follows > xmit_tcb[7] = (int)tx_buff - 0x8000; // internal dma > > address > On simulation time i changed the xmit_tcb[7] only. > The > rest r the same. > > I am confused, since i am getting realtime data with > this initialization. pls expalin ur method and if > possible give ur TCB initialization routine for my > understanding. > > regards > ajith > > --- "Burgwedel, Friedrich" <> > wrote: > > > I had done the chained SPORT DMA in our board. > it > > > is working perfectly without any offsetting. > > > > Yes, the index register is used without offset, > but > > the DMA chain pointer > > register needs the offset. (21065L) > > > > Friedrich > > > > -----Ursprgliche Nachricht----- > > Von: Ajith Kumar P C [mailto:] > > Gesendet: Freitag, 6. Juni 2003 15:28 > > An: Burgwedel, Friedrich; > > Betreff: Re: AW: [adsp] Re: Simulate External > > devices on vdsp > __________________________________ > __________________________________ |
