Waitstates for PM and DM

Dear All,
I am using a SHARC processor (ADSP-21020 ) that has external Data
Memory and Program Memory. I am using external hardware wait state
control for DM and Internal Software controlled wait state for PM
using the DMWAIT and PMWAIT control registers.
I am facing an intriguing problem with different wait sates for DM
and PM when i use assembly code interface with C. Specifically, when i
set the wait state for DM as 3 and that of PM as 2, the assembly
interface logic (of copying constants from PM PROM to DM RAM) does
not do the intended operations. Although, therse is sufficient timing
for memory access, there seems to be some latency issues while
executing memory access instructions simultaneously, which i assume
the compiler (G21k) will take care for different wait sates.
Is there any restriction on programing (in assembly with C) if wait
sates are not same for both PM and DM? Does the programmer need to
take the latency issues in to consideration in such cases?

Awaiting for you valuable response.
regards,
Santanu Start a New Thread

Hi

I want to setup SPI transfer and Im wondering how /CS is manage in DMA
Mode. Is /CS manage for each word transmit, or is /CS manage only at the
beginning (goes low) and at the end (goes high), so /CS i slow during
tranfer of all words (5).

My need is to tranfer 5 word, and manage /CS at the beginning and the end
only : send opcod + adress(2) + data(2).

At this time its working but by managing /CS manually (using flag), but
its problematic in my real time considerations, I want to use SPIFLG staff.

Could you help me on how it works, and if you have example (E2P for example)
?

Thanks in advance Start a New Thread

On Thu, 26 Jun 2008 s...@isac.gov.in wrote:

> Dear All,
> I am using a SHARC processor (ADSP-21020 ) that has external Data
> Memory and Program Memory. I am using external hardware wait state
> control for DM and Internal Software controlled wait state for PM
> using the DMWAIT and PMWAIT control registers.
> I am facing an intriguing problem with different wait sates for DM
> and PM when i use assembly code interface with C. Specifically, when i
> set the wait state for DM as 3 and that of PM as 2, the assembly
> interface logic (of copying constants from PM PROM to DM RAM) does
> not do the intended operations. Although, therse is sufficient timing
> for memory access, there seems to be some latency issues while
> executing memory access instructions simultaneously, which i assume
> the compiler (G21k) will take care for different wait sates.
> Is there any restriction on programing (in assembly with C) if wait
> sates are not same for both PM and DM? Does the programmer need to
> take the latency issues in to consideration in such cases?

I don't know - but making the assumption that G21k will take care of
different wait states isn't possible. The compiler doesn't care about the
hardware. Are there #pragam or command line options you can feed the
compiler to tell it about this? If not, change your code to have one
instruction do the read and a second instruction do the write rather than
just do it in one instruction.

You might also want to check the hardware errata on ADI's web site. There
might not be much you can do other than set PM as 3 wait states, do the
copy, then change it back to 2.

Patience, persistence, truth,
Dr. mike Start a New Thread

Thanks Dr. Mike. I had changed PM and DM to wait sates 3 and the
software is running with few modifications. The observations relates
to different timing margins for memory access in similar hardware (one
with comercial components, other with MIL/Space grade components). As
pointed by you, that the compiler needs the waits state information,
which indeed is available in the architecture file (*.ach), is the
DMWAIT and PMWAIT registers need to be set to proper wait sates as
suggested by you when ever simultaneous access is required?
I found it does the operation even if they are not set to same wait
states. However, i would like to confirm after few more tests.
regards,
Santanu

Quoting Mike Rosing :

> On Thu, 26 Jun 2008 s...@isac.gov.in wrote:
>
>> Dear All,
>> I am using a SHARC processor (ADSP-21020 ) that has external Data
>> Memory and Program Memory. I am using external hardware wait state
>> control for DM and Internal Software controlled wait state for PM
>> using the DMWAIT and PMWAIT control registers.
>> I am facing an intriguing problem with different wait sates for DM
>> and PM when i use assembly code interface with C. Specifically, when i
>> set the wait state for DM as 3 and that of PM as 2, the assembly
>> interface logic (of copying constants from PM PROM to DM RAM) does
>> not do the intended operations. Although, therse is sufficient timing
>> for memory access, there seems to be some latency issues while
>> executing memory access instructions simultaneously, which i assume
>> the compiler (G21k) will take care for different wait sates.
>> Is there any restriction on programing (in assembly with C) if wait
>> sates are not same for both PM and DM? Does the programmer need to
>> take the latency issues in to consideration in such cases?
>
> I don't know - but making the assumption that G21k will take care of
> different wait states isn't possible. The compiler doesn't care about the
> hardware. Are there #pragam or command line options you can feed the
> compiler to tell it about this? If not, change your code to have one
> instruction do the read and a second instruction do the write rather than
> just do it in one instruction.
>
> You might also want to check the hardware errata on ADI's web site. There
> might not be much you can do other than set PM as 3 wait states, do the
> copy, then change it back to 2.
>
> Patience, persistence, truth,
> Dr. mike Start a New Thread