Here's a brief overview of my setup:
I am transferring serial data to and from the AD1939 codecs over 6 data
lines (ADATA x 2, DDATA x 4). Each data line is running in stereo mode,
64 bits per frame. Configuration is managed via SPI, and I've been able
to verify that configuration is correctly sent and received.
The part that is causing me grief is letting the codecs run the BCLK and
LRCLK lines. In the case of the ADC, this isn't a problem. I've
tested
operation in 48 and 96kHz modes. However, with the DAC, both clock
lines go high and stop. Reading back the configuration, I see that the
DAC Configuration Register 1 is reset to default condition - slave mode.
There is a 12.288MHz clock driving MCLKI, so I'm configuring the PLL to
run at 256xFs. I wait for PLL lock before bringing ADC/DAC out of
powerdown.
PLL 0 : 0x98 // MCLKI @ 256xFs; MCLKO Off; PLL from MCLKI; Codecs on
PLL 1 : 0x08 // ADC & DAC clock from PLL; PLL locked
DAC 0 : 0x0A // 96kHz sampling; 1 sample delay; stereo mode
DAC 1 : 0x70 // 64 BCLKs/frame; BCLK & LRCLK master
DAC 2 : 0x00 // 24 bit; unmuted; no filter
ADC 0 : 0x40 // no filter; unmuted; 96kHz sampling
ADC 1 : 0x00 // 24 bit; 1 sample delay; stereo mode
ADC 2 : 0xC8 // 64 BCLKs/frame; BCLK & LRCLK master
I am using SPORT0 for ADC and SPORT1,SPORT2 for DAC, all in I2S mode,
with DMA channels controlling data transfers between memory and the
SPORTs. Data is available and waiting to be clocked out to the DACs
when the powerdown bit is cleared.
If anyone has any insight as to why the DAC does not run as BCLK and
LRCLK master, please let me know. I can't see what I may be
mis-configuring for this to happen.
Cheers,
Greg
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