I am working in custom designed BF561 board. I need a help in SDRAM
controller(SDC).
In my board, two 16bit SDRAM (MT48LC8M16A2 2 Meg x 16 x 4 banks) are
interfaced with bank0(SMS0) of SDC.
SDQM0 and SDQM1 pins are connected to the DQML and DQMH pins of SDRAM1
respectively. And the SDQM2 and SDQM3 pins are connected to the DQML and DQMH
pins of SDRAM2 respectively. SMS0 pin is connected to CS of both SDRAM1 and
SDRAM2.
I have configured the SDRAM registers with the following manner,
*pEBIU_SDBCTL = 0x00000013;
*pEBIU_SDRRC = 0x00000613;
*pEBIU_SDGCTL = 0x00D10159;
In my application, i used to store the 32bit value in SDRAM memory location.
example:
#define START_ADDR 0x00801004
unsigned int *pBuffer ;
unsigned int nData = 10 ;
pBuffer = (unsigned int*) START_ADDR ;
*pBuffer = nData ;
In above example, the value 10 is stored properly in the 0x00801004 memory
location. But the same value is also stored in the 0x00801404 memory location.
This is because of all the SDQM[3:0] pins are enabled through EBIU_SDGCTL
register(From BF561 hardware reference manual).
Q1. Is there any other way to configure/change the state of SDQM pins in
BF561?
Q2. Is there any problem in hardware interface? (i.e. Interfacing two 16bit chip
in same SDRAM bank(SMS0)).
Regards,
palz
