Re: total cycle count and delay in speech (blackfin) (rotate)

Regarding the rotate with CC in Blackfin ... think of it as an extra '33th' bit.

Asume we do a rotate left : you would expect from a true rotate, is that the bit31 becomes bit0, bit0 becomes bit 1, ... However with Blackfin, bit 31 goes into CC, and CC goes into bit 0, bit 0 goes into bit 1, ... (check prog ref manual)

suppose you have r0 = 0x1234567, and you need to move these contents to a byte array, starting with 0x12 first

.byte dummy[4];

r0 = 0x12345678;

p4.l = lo(dummy);
p4.h = hi(dummy); // asume CC = 0 at this point

r0 = rot r0 by 9; // looks strange, but now r0 contains 0x68ACF012
// as you see, the lowest byte is correct. Why does
// the upper part look 'mangled' ... well because CC
// is nog in bitpos '8'. No worries, it will get back
// in place

b[p4++] = ro; // dummy[0] = 0x12;
r0 = rot r0 by 8; // r0 now contains 0xACF01234

b[p4++] = ro; // dummy[1] = 0x34;
r0 = rot r0 by 8; // r0 now contains 0xF0123456

b[p4++] = ro; // dummy[2] = 0x56;

r0 = rot r0 by 8; // r0 now contains (again) 0x12345678
// ain't that somethin' :-)
b[p4] = r0; // dummy[3] = 0x78
> hi,
>I implemented a speech algorithm in pure software using VDSP++4.0 in Blackfin 533 processor.
>I need following important information:
>what is the commonly available frequency of blackfin?
>I assumed it as 500Mhz and got a delay of CCLK = 1133154 = 0.025sec
>I need to know if this is a proper delay.
>
>with regards,
>prasanth
>
>
>
>
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